[LSD] pratica04 CounterDemo enable/disable added and added FreqDevider
by itself
This commit is contained in:
TiagoRG
parent
230fa50257
commit
cf6a13cc90
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@ -31,6 +31,13 @@ https://fpgasoftware.intel.com/eula.
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(text "binInput[3..0]" (rect 21 27 70 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "enable" (rect 0 0 24 12)(font "Arial" ))
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(text "enable" (rect 21 43 45 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 1))
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)
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(port
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(pt 208 32)
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(output)
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@ -4,14 +4,16 @@ use IEEE.STD_LOGIC_1164.all;
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entity Bin7SegDecoder is
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port
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(
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binInput : in std_logic_vector(3 downto 0);
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binInput : in std_logic_vector(3 downto 0);
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enable : in std_logic;
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decOut_n : out std_logic_vector(6 downto 0)
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);
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end Bin7SegDecoder;
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architecture Behavioral of Bin7SegDecoder is
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begin
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decOut_n <= "1111001" when (binInput = "0001") else --1
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decOut_n <= "0111111" when (enable = '0' ) else -- disabled
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"1111001" when (binInput = "0001") else --1
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"0100100" when (binInput = "0010") else --2
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"0110000" when (binInput = "0011") else --3
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"0011001" when (binInput = "0100") else --4
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@ -27,4 +29,4 @@ begin
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"0000110" when (binInput = "1110") else --E
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"0001110" when (binInput = "1111") else --F
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"1000000"; --0
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end Behavioral;
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end Behavioral;
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@ -20,23 +20,6 @@ refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "graphic" (version "1.4"))
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(pin
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(input)
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(rect 256 232 424 248)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "KEY[1]" (rect 5 0 39 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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(line (pt 84 4)(pt 109 4))
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(line (pt 113 8)(pt 168 8))
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(line (pt 84 12)(pt 84 4))
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(line (pt 109 4)(pt 113 8))
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(line (pt 109 12)(pt 113 8))
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)
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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(annotation_block (location)(rect 192 248 256 264))
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)
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(pin
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(input)
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(rect 256 248 424 264)
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@ -58,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
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(input)
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(rect 152 176 320 192)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "CLOCK_50" (rect 5 0 63 11)(font "Arial" ))
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(text "CLOCK_50" (rect 5 0 62 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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@ -71,9 +54,43 @@ https://fpgasoftware.intel.com/eula.
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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(annotation_block (location)(rect 88 192 152 208))
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)
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(pin
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(input)
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(rect 496 304 664 320)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "SW[1]" (rect 5 0 36 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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(line (pt 84 4)(pt 109 4))
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(line (pt 113 8)(pt 168 8))
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(line (pt 84 12)(pt 84 4))
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(line (pt 109 4)(pt 113 8))
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(line (pt 109 12)(pt 113 8))
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)
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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(annotation_block (location)(rect 496 320 560 336))
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)
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(pin
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(input)
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(rect 256 232 424 248)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "KEY[0]" (rect 5 0 40 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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(line (pt 84 4)(pt 109 4))
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(line (pt 113 8)(pt 168 8))
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(line (pt 84 12)(pt 84 4))
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(line (pt 109 4)(pt 113 8))
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(line (pt 109 12)(pt 113 8))
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)
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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(annotation_block (location)(rect 192 248 256 264))
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)
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(pin
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(output)
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(rect 872 216 1048 232)
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(rect 896 216 1072 232)
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(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
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(text "HEX0[6..0]" (rect 90 0 144 11)(font "Arial" ))
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(pt 0 8)
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@ -86,7 +103,7 @@ https://fpgasoftware.intel.com/eula.
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(line (pt 82 8)(pt 78 12))
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(line (pt 78 12)(pt 82 8))
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)
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(annotation_block (location)(rect 1048 232 1112 248))
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(annotation_block (location)(rect 1072 232 1136 248))
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)
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(symbol
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(rect 432 224 480 256)
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@ -113,28 +130,6 @@ https://fpgasoftware.intel.com/eula.
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(circle (rect 31 12 39 20))
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)
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)
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(symbol
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(rect 672 192 880 272)
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(text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" ))
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(text "hex" (rect 8 64 28 75)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" ))
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(text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 208 32)
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(output)
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(text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" ))
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(text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" ))
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(line (pt 208 32)(pt 192 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 192 64))
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)
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)
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(symbol
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(rect 488 192 664 304)
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(text "CounterUpDown4" (rect 5 0 94 11)(font "Arial" ))
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@ -193,6 +188,35 @@ https://fpgasoftware.intel.com/eula.
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(rectangle (rect 16 16 128 64))
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)
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)
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(symbol
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(rect 680 192 888 272)
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(text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" ))
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(text "inst4" (rect 8 64 33 77)(font "Intel Clear" ))
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(port
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(pt 0 32)
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(input)
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(text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" ))
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(text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "enable" (rect 0 0 34 11)(font "Arial" ))
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(text "enable" (rect 21 43 55 54)(font "Arial" ))
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(line (pt 0 48)(pt 16 48))
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)
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(port
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(pt 208 32)
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(output)
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(text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" ))
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(text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" ))
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(line (pt 208 32)(pt 192 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 192 64))
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)
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)
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(connector
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(pt 480 224)
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(pt 488 224)
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@ -205,16 +229,6 @@ https://fpgasoftware.intel.com/eula.
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(pt 432 240)
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(pt 424 240)
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)
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(connector
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(pt 664 224)
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(pt 672 224)
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(bus)
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)
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(connector
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(pt 872 224)
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(pt 880 224)
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(bus)
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)
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(connector
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(pt 424 256)
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(pt 488 256)
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@ -231,3 +245,25 @@ https://fpgasoftware.intel.com/eula.
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(pt 328 184)
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(pt 320 184)
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)
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(connector
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(pt 664 224)
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(pt 680 224)
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(bus)
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)
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(connector
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(pt 888 224)
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(pt 896 224)
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(bus)
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)
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(connector
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(pt 680 240)
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(pt 672 240)
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)
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(connector
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(pt 664 312)
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(pt 672 312)
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)
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(connector
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(pt 672 240)
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(pt 672 312)
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)
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Binary file not shown.
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@ -0,0 +1,145 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FreqDivider_Demo -c FreqDivider_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDevider.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/FreqDevider.vwf.vht"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FreqDivider_Demo -c FreqDivider_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDevider.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/FreqDevider.vwf.vht"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/" FreqDivider_Demo -c FreqDivider_Demo</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/" FreqDivider_Demo -c FreqDivider_Demo</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vcom -work work FreqDivider_Demo.vho
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vcom -work work FreqDevider.vwf.vht
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vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FreqDivider_vhd_vec_tst
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vcd file -direction FreqDivider_Demo.msim.vcd
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vcd add -internal FreqDivider_vhd_vec_tst/*
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vcd add -internal FreqDivider_vhd_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vcom -work work FreqDivider_Demo.vho
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vcom -work work FreqDevider.vwf.vht
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vsim -novopt -c -t 1ps -sdfmax FreqDivider_vhd_vec_tst/i1=FreqDivider_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FreqDivider_vhd_vec_tst
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vcd file -direction FreqDivider_Demo.msim.vcd
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vcd add -internal FreqDivider_vhd_vec_tst/*
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vcd add -internal FreqDivider_vhd_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>vhdl</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("clkIn")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("clkOut")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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TRANSITION_LIST("clkIn")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 50;
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LEVEL 0 FOR 10.0;
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LEVEL 1 FOR 10.0;
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}
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}
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}
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TRANSITION_LIST("clkOut")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "clkIn";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 0;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "clkOut";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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TREE_LEVEL = 0;
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}
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TIME_BAR
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{
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TIME = 0;
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MASTER = TRUE;
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}
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;
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@ -0,0 +1,44 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 160 96)
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(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
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(text "inst" (rect 8 64 20 76)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
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(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 144 32)
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(output)
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(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
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(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
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(line (pt 144 32)(pt 128 32)(line_width 1))
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)
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(drawing
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(rectangle (rect 16 16 128 64)(line_width 1))
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)
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)
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@ -0,0 +1,33 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.NUMERIC_STD.all;
|
||||
|
||||
entity FreqDivider is
|
||||
port (clkIn : in std_logic;
|
||||
clkOut : out std_logic
|
||||
);
|
||||
end FreqDivider;
|
||||
|
||||
architecture Behavioral of FreqDivider is
|
||||
signal s_counter : unsigned(31 downto 0);
|
||||
signal s_halfWay : unsigned(31 downto 0);
|
||||
signal k : std_logic_vector(31 downto 0);
|
||||
begin
|
||||
k <= x"017D7840";
|
||||
s_halfWay <= unsigned(k);
|
||||
|
||||
process(clkIn)
|
||||
begin
|
||||
if (rising_edge(clkIn)) then
|
||||
if (s_counter = s_halfWay - 1) then
|
||||
clkOut <= '0';
|
||||
s_counter <= (others => '0');
|
||||
else
|
||||
if (s_counter = s_halfWay/2 - 1) then
|
||||
clkOut <= '1';
|
||||
end if;
|
||||
s_counter <= s_counter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 304 192 472 208)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "CLOCK_50" (rect 5 0 63 11)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 632 192 808 208)
|
||||
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
|
||||
(text "LEDR[0]" (rect 90 0 132 11)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 480 168 624 248)
|
||||
(text "FreqDivider" (rect 5 0 64 11)(font "Arial" ))
|
||||
(text "inst" (rect 8 64 26 75)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clkIn" (rect 0 0 24 11)(font "Arial" ))
|
||||
(text "clkIn" (rect 21 27 45 38)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 144 32)
|
||||
(output)
|
||||
(text "clkOut" (rect 0 0 33 11)(font "Arial" ))
|
||||
(text "clkOut" (rect 96 27 129 38)(font "Arial" ))
|
||||
(line (pt 144 32)(pt 128 32))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 128 64))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 472 200)
|
||||
(pt 480 200)
|
||||
)
|
||||
(connector
|
||||
(pt 632 200)
|
||||
(pt 624 200)
|
||||
)
|
||||
Binary file not shown.
Loading…
Reference in New Issue