diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.bsf b/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.bsf index bedfb17..2cc9938 100644 --- a/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.bsf +++ b/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.bsf @@ -31,6 +31,13 @@ https://fpgasoftware.intel.com/eula. (text "binInput[3..0]" (rect 21 27 70 39)(font "Arial" )) (line (pt 0 32)(pt 16 32)(line_width 3)) ) + (port + (pt 0 48) + (input) + (text "enable" (rect 0 0 24 12)(font "Arial" )) + (text "enable" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) (port (pt 208 32) (output) diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd index f3e8536..6ad6947 100644 --- a/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd +++ b/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd @@ -4,14 +4,16 @@ use IEEE.STD_LOGIC_1164.all; entity Bin7SegDecoder is port ( - binInput : in std_logic_vector(3 downto 0); + binInput : in std_logic_vector(3 downto 0); + enable : in std_logic; decOut_n : out std_logic_vector(6 downto 0) ); end Bin7SegDecoder; architecture Behavioral of Bin7SegDecoder is begin - decOut_n <= "1111001" when (binInput = "0001") else --1 + decOut_n <= "0111111" when (enable = '0' ) else -- disabled + "1111001" when (binInput = "0001") else --1 "0100100" when (binInput = "0010") else --2 "0110000" when (binInput = "0011") else --3 "0011001" when (binInput = "0100") else --4 @@ -27,4 +29,4 @@ begin "0000110" when (binInput = "1110") else --E "0001110" when (binInput = "1111") else --F "1000000"; --0 -end Behavioral; \ No newline at end of file +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf index a095895..e753031 100644 --- a/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf +++ b/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf @@ -20,23 +20,6 @@ refer to the applicable agreement for further details, at https://fpgasoftware.intel.com/eula. */ (header "graphic" (version "1.4")) -(pin - (input) - (rect 256 232 424 248) - (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) - (text "KEY[1]" (rect 5 0 39 11)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 84 12)(pt 109 12)) - (line (pt 84 4)(pt 109 4)) - (line (pt 113 8)(pt 168 8)) - (line (pt 84 12)(pt 84 4)) - (line (pt 109 4)(pt 113 8)) - (line (pt 109 12)(pt 113 8)) - ) - (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 192 248 256 264)) -) (pin (input) (rect 256 248 424 264) @@ -58,7 +41,7 @@ https://fpgasoftware.intel.com/eula. (input) (rect 152 176 320 192) (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) - (text "CLOCK_50" (rect 5 0 63 11)(font "Arial" )) + (text "CLOCK_50" (rect 5 0 62 11)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -71,9 +54,43 @@ https://fpgasoftware.intel.com/eula. (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) (annotation_block (location)(rect 88 192 152 208)) ) +(pin + (input) + (rect 496 304 664 320) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[1]" (rect 5 0 36 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 496 320 560 336)) +) +(pin + (input) + (rect 256 232 424 248) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "KEY[0]" (rect 5 0 40 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 192 248 256 264)) +) (pin (output) - (rect 872 216 1048 232) + (rect 896 216 1072 232) (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "HEX0[6..0]" (rect 90 0 144 11)(font "Arial" )) (pt 0 8) @@ -86,7 +103,7 @@ https://fpgasoftware.intel.com/eula. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 1048 232 1112 248)) + (annotation_block (location)(rect 1072 232 1136 248)) ) (symbol (rect 432 224 480 256) @@ -113,28 +130,6 @@ https://fpgasoftware.intel.com/eula. (circle (rect 31 12 39 20)) ) ) -(symbol - (rect 672 192 880 272) - (text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" )) - (text "hex" (rect 8 64 28 75)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" )) - (text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" )) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 208 32) - (output) - (text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" )) - (text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" )) - (line (pt 208 32)(pt 192 32)(line_width 3)) - ) - (drawing - (rectangle (rect 16 16 192 64)) - ) -) (symbol (rect 488 192 664 304) (text "CounterUpDown4" (rect 5 0 94 11)(font "Arial" )) @@ -193,6 +188,35 @@ https://fpgasoftware.intel.com/eula. (rectangle (rect 16 16 128 64)) ) ) +(symbol + (rect 680 192 888 272) + (text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" )) + (text "inst4" (rect 8 64 33 77)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" )) + (text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "enable" (rect 0 0 34 11)(font "Arial" )) + (text "enable" (rect 21 43 55 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 208 32) + (output) + (text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" )) + (text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" )) + (line (pt 208 32)(pt 192 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 192 64)) + ) +) (connector (pt 480 224) (pt 488 224) @@ -205,16 +229,6 @@ https://fpgasoftware.intel.com/eula. (pt 432 240) (pt 424 240) ) -(connector - (pt 664 224) - (pt 672 224) - (bus) -) -(connector - (pt 872 224) - (pt 880 224) - (bus) -) (connector (pt 424 256) (pt 488 256) @@ -231,3 +245,25 @@ https://fpgasoftware.intel.com/eula. (pt 328 184) (pt 320 184) ) +(connector + (pt 664 224) + (pt 680 224) + (bus) +) +(connector + (pt 888 224) + (pt 896 224) + (bus) +) +(connector + (pt 680 240) + (pt 672 240) +) +(connector + (pt 664 312) + (pt 672 312) +) +(connector + (pt 672 240) + (pt 672 312) +) diff --git a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sof b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sof index 2459abd..f23d17f 100644 Binary files a/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sof and b/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sof differ diff --git a/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDevider.vwf b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDevider.vwf new file mode 100644 index 0000000..57551f6 --- /dev/null +++ b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDevider.vwf @@ -0,0 +1,145 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FreqDivider_Demo -c FreqDivider_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDevider.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/FreqDevider.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FreqDivider_Demo -c FreqDivider_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDevider.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/FreqDevider.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/" FreqDivider_Demo -c FreqDivider_Demo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/simulation/qsim/" FreqDivider_Demo -c FreqDivider_Demo +onerror {exit -code 1} +vlib work +vcom -work work FreqDivider_Demo.vho +vcom -work work FreqDevider.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FreqDivider_vhd_vec_tst +vcd file -direction FreqDivider_Demo.msim.vcd +vcd add -internal FreqDivider_vhd_vec_tst/* +vcd add -internal FreqDivider_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work FreqDivider_Demo.vho +vcom -work work FreqDevider.vwf.vht +vsim -novopt -c -t 1ps -sdfmax FreqDivider_vhd_vec_tst/i1=FreqDivider_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FreqDivider_vhd_vec_tst +vcd file -direction FreqDivider_Demo.msim.vcd +vcd add -internal FreqDivider_vhd_vec_tst/* +vcd add -internal FreqDivider_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clkIn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clkOut") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clkIn") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("clkOut") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clkIn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clkOut"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider.bsf b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider.bsf new file mode 100644 index 0000000..76b5c9e --- /dev/null +++ b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider.bsf @@ -0,0 +1,44 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 160 96) + (text "FreqDivider" (rect 5 0 52 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clkIn" (rect 0 0 17 12)(font "Arial" )) + (text "clkIn" (rect 21 27 38 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 144 32) + (output) + (text "clkOut" (rect 0 0 24 12)(font "Arial" )) + (text "clkOut" (rect 99 27 123 39)(font "Arial" )) + (line (pt 144 32)(pt 128 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 128 64)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider.vhd b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider.vhd new file mode 100644 index 0000000..9eb9d16 --- /dev/null +++ b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider.vhd @@ -0,0 +1,33 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity FreqDivider is + port (clkIn : in std_logic; + clkOut : out std_logic + ); +end FreqDivider; + +architecture Behavioral of FreqDivider is + signal s_counter : unsigned(31 downto 0); + signal s_halfWay : unsigned(31 downto 0); + signal k : std_logic_vector(31 downto 0); +begin + k <= x"017D7840"; + s_halfWay <= unsigned(k); + + process(clkIn) + begin + if (rising_edge(clkIn)) then + if (s_counter = s_halfWay - 1) then + clkOut <= '0'; + s_counter <= (others => '0'); + else + if (s_counter = s_halfWay/2 - 1) then + clkOut <= '1'; + end if; + s_counter <= s_counter + 1; + end if; + end if; + end process; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider_Demo.bdf b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider_Demo.bdf new file mode 100644 index 0000000..e39f1a5 --- /dev/null +++ b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/FreqDivider_Demo.bdf @@ -0,0 +1,84 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 304 192 472 208) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "CLOCK_50" (rect 5 0 63 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 632 192 808 208) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[0]" (rect 90 0 132 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 480 168 624 248) + (text "FreqDivider" (rect 5 0 64 11)(font "Arial" )) + (text "inst" (rect 8 64 26 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clkIn" (rect 0 0 24 11)(font "Arial" )) + (text "clkIn" (rect 21 27 45 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 144 32) + (output) + (text "clkOut" (rect 0 0 33 11)(font "Arial" )) + (text "clkOut" (rect 96 27 129 38)(font "Arial" )) + (line (pt 144 32)(pt 128 32)) + ) + (drawing + (rectangle (rect 16 16 128 64)) + ) +) +(connector + (pt 472 200) + (pt 480 200) +) +(connector + (pt 632 200) + (pt 624 200) +) diff --git a/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/output_files/FreqDivider_Demo.sof b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/output_files/FreqDivider_Demo.sof new file mode 100644 index 0000000..2bdb3f8 Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/FreqDivider_Demo/output_files/FreqDivider_Demo.sof differ