119 lines
3.1 KiB
VHDL
119 lines
3.1 KiB
VHDL
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- VENDOR "Altera"
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-- PROGRAM "Quartus Prime"
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-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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-- DATE "02/18/2023 15:33:49"
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--
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-- Device: Altera EP4CE115F29C7 Package FBGA780
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--
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--
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-- This VHDL file should be used for ModelSim-Altera (VHDL) only
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--
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY AND2Gate IS
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PORT (
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inPort0 : IN std_logic;
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inPort1 : IN std_logic;
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outPort : OUT std_logic
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);
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END AND2Gate;
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ARCHITECTURE structure OF AND2Gate IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL devoe : std_logic := '1';
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SIGNAL devclrn : std_logic := '1';
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SIGNAL devpor : std_logic := '1';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL ww_inPort0 : std_logic;
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SIGNAL ww_inPort1 : std_logic;
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SIGNAL ww_outPort : std_logic;
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SIGNAL \outPort~output_o\ : std_logic;
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SIGNAL \inPort0~input_o\ : std_logic;
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SIGNAL \inPort1~input_o\ : std_logic;
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SIGNAL \outPort~0_combout\ : std_logic;
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BEGIN
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ww_inPort0 <= inPort0;
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ww_inPort1 <= inPort1;
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outPort <= ww_outPort;
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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\outPort~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \outPort~0_combout\,
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devoe => ww_devoe,
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o => \outPort~output_o\);
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\inPort0~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_inPort0,
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o => \inPort0~input_o\);
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\inPort1~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_inPort1,
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o => \inPort1~input_o\);
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\outPort~0\ : cycloneive_lcell_comb
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-- Equation(s):
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-- \outPort~0_combout\ = (\inPort0~input_o\ & \inPort1~input_o\)
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "1000100010001000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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dataa => \inPort0~input_o\,
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datab => \inPort1~input_o\,
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combout => \outPort~0_combout\);
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ww_outPort <= \outPort~output_o\;
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END structure;
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