TiagoRG 4fbb93468b LSD aula01 initial commit, base VHDL files, to be finished along the hardware		2023-02-20 22:37:38 +00:00
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work	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.sft	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.vho	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.vwf.vht	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate_modelsim.xrf	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
VHDLDemo.do	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
VHDLDemo.msim.vcd	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
VHDLDemo_20230218153350.sim.vwf	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
transcript	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
vwf_sim_transcript	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00