295 lines
7.3 KiB
Plaintext
295 lines
7.3 KiB
Plaintext
// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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// DATE "11/14/2022 21:42:11"
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//
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// Device: Altera EP4CE6E22C6 Package TQFP144
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//
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//
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// This Verilog file should be used for ModelSim-Altera (Verilog) only
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//
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`timescale 1 ps/ 1 ps
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module Dec2_4 (
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Y3,
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E0L,
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E1,
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X1,
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X0,
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Y2,
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Y1,
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Y0);
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output Y3;
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input E0L;
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input E1;
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input X1;
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input X0;
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output Y2;
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output Y1;
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output Y0;
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// Design Ports Information
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// Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default
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// Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default
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// Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default
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// Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default
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// E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default
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// X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default
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// X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default
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// E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \Y3~output_o ;
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wire \Y2~output_o ;
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wire \Y1~output_o ;
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wire \Y0~output_o ;
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wire \E1~input_o ;
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wire \X1~input_o ;
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wire \X0~input_o ;
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wire \E0L~input_o ;
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wire \inst~combout ;
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wire \inst1~combout ;
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wire \inst3~combout ;
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wire \inst2~combout ;
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hard_block auto_generated_inst(
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.devpor(devpor),
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.devclrn(devclrn),
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.devoe(devoe));
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// Location: IOOBUF_X0_Y6_N23
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cycloneive_io_obuf \Y3~output (
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.i(\inst~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\Y3~output_o ),
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.obar());
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// synopsys translate_off
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defparam \Y3~output .bus_hold = "false";
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defparam \Y3~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOOBUF_X0_Y6_N16
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cycloneive_io_obuf \Y2~output (
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.i(\inst1~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\Y2~output_o ),
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.obar());
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// synopsys translate_off
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defparam \Y2~output .bus_hold = "false";
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defparam \Y2~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOOBUF_X0_Y9_N9
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cycloneive_io_obuf \Y1~output (
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.i(\inst3~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\Y1~output_o ),
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.obar());
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// synopsys translate_off
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defparam \Y1~output .bus_hold = "false";
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defparam \Y1~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOOBUF_X0_Y5_N16
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cycloneive_io_obuf \Y0~output (
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.i(\inst2~combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\Y0~output_o ),
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.obar());
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// synopsys translate_off
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defparam \Y0~output .bus_hold = "false";
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defparam \Y0~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOIBUF_X0_Y11_N15
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cycloneive_io_ibuf \E1~input (
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.i(E1),
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.ibar(gnd),
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.o(\E1~input_o ));
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// synopsys translate_off
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defparam \E1~input .bus_hold = "false";
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defparam \E1~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X0_Y7_N1
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cycloneive_io_ibuf \X1~input (
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.i(X1),
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.ibar(gnd),
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.o(\X1~input_o ));
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// synopsys translate_off
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defparam \X1~input .bus_hold = "false";
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defparam \X1~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X0_Y11_N22
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cycloneive_io_ibuf \X0~input (
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.i(X0),
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.ibar(gnd),
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.o(\X0~input_o ));
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// synopsys translate_off
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defparam \X0~input .bus_hold = "false";
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defparam \X0~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X0_Y8_N15
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cycloneive_io_ibuf \E0L~input (
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.i(E0L),
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.ibar(gnd),
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.o(\E0L~input_o ));
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// synopsys translate_off
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defparam \E0L~input .bus_hold = "false";
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defparam \E0L~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X6_Y9_N8
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cycloneive_lcell_comb inst(
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// Equation(s):
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// \inst~combout = (\E1~input_o & (!\X1~input_o & (!\X0~input_o & !\E0L~input_o )))
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.dataa(\E1~input_o ),
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.datab(\X1~input_o ),
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.datac(\X0~input_o ),
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.datad(\E0L~input_o ),
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.cin(gnd),
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.combout(\inst~combout ),
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.cout());
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// synopsys translate_off
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defparam inst.lut_mask = 16'h0002;
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defparam inst.sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X6_Y9_N2
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cycloneive_lcell_comb inst1(
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// Equation(s):
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// \inst1~combout = (\E1~input_o & (!\X1~input_o & (\X0~input_o & !\E0L~input_o )))
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.dataa(\E1~input_o ),
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.datab(\X1~input_o ),
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.datac(\X0~input_o ),
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.datad(\E0L~input_o ),
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.cin(gnd),
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.combout(\inst1~combout ),
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.cout());
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// synopsys translate_off
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defparam inst1.lut_mask = 16'h0020;
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defparam inst1.sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X6_Y9_N28
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cycloneive_lcell_comb inst3(
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// Equation(s):
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// \inst3~combout = (\E1~input_o & (\X1~input_o & (\X0~input_o & !\E0L~input_o )))
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.dataa(\E1~input_o ),
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.datab(\X1~input_o ),
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.datac(\X0~input_o ),
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.datad(\E0L~input_o ),
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.cin(gnd),
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.combout(\inst3~combout ),
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.cout());
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// synopsys translate_off
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defparam inst3.lut_mask = 16'h0080;
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defparam inst3.sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X6_Y9_N30
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cycloneive_lcell_comb inst2(
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// Equation(s):
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// \inst2~combout = (\E1~input_o & (\X1~input_o & (!\X0~input_o & !\E0L~input_o )))
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.dataa(\E1~input_o ),
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.datab(\X1~input_o ),
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.datac(\X0~input_o ),
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.datad(\E0L~input_o ),
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.cin(gnd),
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.combout(\inst2~combout ),
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.cout());
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// synopsys translate_off
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defparam inst2.lut_mask = 16'h0008;
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defparam inst2.sum_lutc_input = "datac";
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// synopsys translate_on
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assign Y3 = \Y3~output_o ;
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assign Y2 = \Y2~output_o ;
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assign Y1 = \Y1~output_o ;
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assign Y0 = \Y0~output_o ;
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endmodule
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module hard_block (
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devpor,
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devclrn,
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devoe);
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// Design Ports Information
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// ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA
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input devpor;
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input devclrn;
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input devoe;
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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wire \~ALTERA_ASDO_DATA1~~padout ;
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wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
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wire \~ALTERA_DATA0~~padout ;
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wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
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wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
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wire \~ALTERA_DATA0~~ibuf_o ;
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endmodule
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