uaveiro-leci/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.vo

// Copyright (C) 2020  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"

// DATE "11/14/2022 21:42:11"

// 
// Device: Altera EP4CE6E22C6 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module Dec2_4 (
	Y3,
	E0L,
	E1,
	X1,
	X0,
	Y2,
	Y1,
	Y0);
output 	Y3;
input 	E0L;
input 	E1;
input 	X1;
input 	X0;
output 	Y2;
output 	Y1;
output 	Y0;

// Design Ports Information
// Y3	=>  Location: PIN_33,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Y2	=>  Location: PIN_32,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Y1	=>  Location: PIN_28,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Y0	=>  Location: PIN_34,	 I/O Standard: 2.5 V,	 Current Strength: Default
// E1	=>  Location: PIN_24,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X0	=>  Location: PIN_25,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X1	=>  Location: PIN_31,	 I/O Standard: 2.5 V,	 Current Strength: Default
// E0L	=>  Location: PIN_30,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \Y3~output_o ;
wire \Y2~output_o ;
wire \Y1~output_o ;
wire \Y0~output_o ;
wire \E1~input_o ;
wire \X1~input_o ;
wire \X0~input_o ;
wire \E0L~input_o ;
wire \inst~combout ;
wire \inst1~combout ;
wire \inst3~combout ;
wire \inst2~combout ;


hard_block auto_generated_inst(
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// Location: IOOBUF_X0_Y6_N23
cycloneive_io_obuf \Y3~output (
	.i(\inst~combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Y3~output_o ),
	.obar());
// synopsys translate_off
defparam \Y3~output .bus_hold = "false";
defparam \Y3~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y6_N16
cycloneive_io_obuf \Y2~output (
	.i(\inst1~combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Y2~output_o ),
	.obar());
// synopsys translate_off
defparam \Y2~output .bus_hold = "false";
defparam \Y2~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y9_N9
cycloneive_io_obuf \Y1~output (
	.i(\inst3~combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Y1~output_o ),
	.obar());
// synopsys translate_off
defparam \Y1~output .bus_hold = "false";
defparam \Y1~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOOBUF_X0_Y5_N16
cycloneive_io_obuf \Y0~output (
	.i(\inst2~combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Y0~output_o ),
	.obar());
// synopsys translate_off
defparam \Y0~output .bus_hold = "false";
defparam \Y0~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X0_Y11_N15
cycloneive_io_ibuf \E1~input (
	.i(E1),
	.ibar(gnd),
	.o(\E1~input_o ));
// synopsys translate_off
defparam \E1~input .bus_hold = "false";
defparam \E1~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y7_N1
cycloneive_io_ibuf \X1~input (
	.i(X1),
	.ibar(gnd),
	.o(\X1~input_o ));
// synopsys translate_off
defparam \X1~input .bus_hold = "false";
defparam \X1~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y11_N22
cycloneive_io_ibuf \X0~input (
	.i(X0),
	.ibar(gnd),
	.o(\X0~input_o ));
// synopsys translate_off
defparam \X0~input .bus_hold = "false";
defparam \X0~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y8_N15
cycloneive_io_ibuf \E0L~input (
	.i(E0L),
	.ibar(gnd),
	.o(\E0L~input_o ));
// synopsys translate_off
defparam \E0L~input .bus_hold = "false";
defparam \E0L~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X6_Y9_N8
cycloneive_lcell_comb inst(
// Equation(s):
// \inst~combout  = (\E1~input_o  & (!\X1~input_o  & (!\X0~input_o  & !\E0L~input_o )))

	.dataa(\E1~input_o ),
	.datab(\X1~input_o ),
	.datac(\X0~input_o ),
	.datad(\E0L~input_o ),
	.cin(gnd),
	.combout(\inst~combout ),
	.cout());
// synopsys translate_off
defparam inst.lut_mask = 16'h0002;
defparam inst.sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X6_Y9_N2
cycloneive_lcell_comb inst1(
// Equation(s):
// \inst1~combout  = (\E1~input_o  & (!\X1~input_o  & (\X0~input_o  & !\E0L~input_o )))

	.dataa(\E1~input_o ),
	.datab(\X1~input_o ),
	.datac(\X0~input_o ),
	.datad(\E0L~input_o ),
	.cin(gnd),
	.combout(\inst1~combout ),
	.cout());
// synopsys translate_off
defparam inst1.lut_mask = 16'h0020;
defparam inst1.sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X6_Y9_N28
cycloneive_lcell_comb inst3(
// Equation(s):
// \inst3~combout  = (\E1~input_o  & (\X1~input_o  & (\X0~input_o  & !\E0L~input_o )))

	.dataa(\E1~input_o ),
	.datab(\X1~input_o ),
	.datac(\X0~input_o ),
	.datad(\E0L~input_o ),
	.cin(gnd),
	.combout(\inst3~combout ),
	.cout());
// synopsys translate_off
defparam inst3.lut_mask = 16'h0080;
defparam inst3.sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X6_Y9_N30
cycloneive_lcell_comb inst2(
// Equation(s):
// \inst2~combout  = (\E1~input_o  & (\X1~input_o  & (!\X0~input_o  & !\E0L~input_o )))

	.dataa(\E1~input_o ),
	.datab(\X1~input_o ),
	.datac(\X0~input_o ),
	.datad(\E0L~input_o ),
	.cin(gnd),
	.combout(\inst2~combout ),
	.cout());
// synopsys translate_off
defparam inst2.lut_mask = 16'h0008;
defparam inst2.sum_lutc_input = "datac";
// synopsys translate_on

assign Y3 = \Y3~output_o ;

assign Y2 = \Y2~output_o ;

assign Y1 = \Y1~output_o ;

assign Y0 = \Y0~output_o ;

endmodule

module hard_block (

	devpor,
	devclrn,
	devoe);

// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_101,	 I/O Standard: 2.5 V,	 Current Strength: 8mA

input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

wire \~ALTERA_ASDO_DATA1~~padout ;
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
wire \~ALTERA_DATA0~~padout ;
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
wire \~ALTERA_DATA0~~ibuf_o ;


endmodule