Commit Graph

53 Commits

Author SHA1 Message Date
TiagoRG cfa4ab4a84 [LSD] added ALUDemo version using displays (pratica03 - part3) 2023-04-05 14:35:27 +01:00
TiagoRG d364a38abc [LSD] added generic version to ALUDemo (pratica05 - part5) 2023-04-05 14:34:11 +01:00
TiagoRG 21266306fa [LSD] BasicWatch added (pratica05 | part4) 2023-04-05 12:24:35 +01:00
TiagoRG cf6a13cc90 [LSD] pratica04 CounterDemo enable/disable added and added FreqDevider
by itself
2023-04-04 22:06:30 +01:00
TiagoRG fd54e7341d [LSD] pratica05 part3 added 2023-04-04 18:24:18 +01:00
TiagoRG 622f3b0eb1 [LSD] README update 2023-04-04 18:20:08 +01:00
TiagoRG 6ec02f0569 [LSD] material added 2023-04-04 18:17:34 +01:00
TiagoRG 7eea3c7abb [LSD] pratica06 part1 added (with enable and direction selector included) 2023-03-29 13:06:32 +01:00
TiagoRG 9f8717a207 [LSD] pratica06 guide added 2023-03-29 12:08:56 +01:00
TiagoRG 60947591ac [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
TiagoRG b90732d034 [LSD] Removed unnecessary directories (big commit) 2023-03-28 23:46:49 +01:00
TiagoRG b36275c654 [LSD] changed the timer value 2023-03-28 15:25:43 +01:00
TiagoRG 65487cae03 [LSD] compilation cache 2023-03-24 18:45:52 +00:00
TiagoRG a0bf82237f [LSD] pratica05 part2 added 2023-03-22 12:52:09 +00:00
TiagoRG c1976d312f [LSD] compilation cache 2023-03-22 12:51:53 +00:00
TiagoRG 2de5e44e7f [LSD] pratica04 part2 added 2023-03-22 09:20:58 +00:00
TiagoRG 715510bcb3 [LSD] pratica05 part1 added 2023-03-21 22:41:33 +00:00
TiagoRG 8ccc00cdd5 [LSD] guide for pratica05 added 2023-03-21 22:41:18 +00:00
TiagoRG 612cdde175 [LSD] pratica04 part3 added 2023-03-21 22:40:05 +00:00
TiagoRG 6e1c945522 [LSD] pratica04 part1 added 2023-03-21 22:39:46 +00:00
TiagoRG b772d7ffc4 [LSD] guide for pratica04 added 2023-03-21 22:39:29 +00:00
TiagoRG cbbcdf4f28 [LSD] pratica03 part2 finished (in theory at least 💀) 2023-03-16 16:36:47 +00:00
TiagoRG 5d04683479 [LSD] pratica03 part1 fix 2023-03-16 14:49:40 +00:00
TiagoRG 72c0efc44c [LSD] pratica03 part1 concluded 2023-03-09 17:08:58 +00:00
TiagoRG 54f6e6cea8 [LSD] pratica02 parts 1,2,3 concluded 2023-03-09 10:18:38 +00:00
TiagoRG cc20f6b529 [LSD] DisplayDemo using VHDL finished 2023-03-08 20:58:26 +00:00
TiagoRG 92ff342766 [LSD] slides for TP04 added 2023-03-08 20:53:22 +00:00
TiagoRG f43e3b59f0 [LSD] DisplayDemo using block diagram finished 2023-03-08 20:52:48 +00:00
TiagoRG b896cb9f3b [LSD] DisplayDemo using block diagram finished 2023-03-08 20:07:34 +00:00
TiagoRG ee5253ff18 [LSD] Mux2_1 finished 2023-03-08 19:52:17 +00:00
TiagoRG 81663d235e [LSD] pratica02 part2 added (untested) 2023-03-07 23:07:36 +00:00
TiagoRG 6f7cc2ed2a [LSD] Compiled pratica01 part2 2023-03-07 23:07:02 +00:00
TiagoRG 407b0da901 [LSD] Removed unnecessary master.qsf files 2023-03-07 23:05:32 +00:00
TiagoRG 654d465fff [LSD] Recreated master.qsf at lsd root 2023-03-07 23:00:18 +00:00
TiagoRG 52c622411d [LSD] pratica01 part2 block diagram version of NAND2Gate 2023-03-07 21:00:18 +00:00
TiagoRG 275257b3af [LSD] pratica01 part3 simulation waveform created 2023-03-07 20:59:42 +00:00
TiagoRG f884503b3f [LSD] pratica01 part4 finished (untested) 2023-03-07 20:59:22 +00:00
TiagoRG ab264ce917 [LSD] pratica01 part4 finished 2023-03-07 19:02:31 +00:00
TiagoRG bfb90fa718 [LSD] Removed master.qsf from lsd root 2023-03-07 18:04:24 +00:00
TiagoRG 63d832a8d2 [LSD] pratica01 part3 added 2023-03-06 15:31:27 +00:00
TiagoRG 83605aca6d LSD refactor: aulaX to praticaX 2023-03-02 19:08:05 +00:00
TiagoRG bdff37a4c8 LSD aula02 part1 finished 2023-03-01 12:50:07 +00:00
TiagoRG af7fac2074 LSD README update 2023-03-01 12:19:44 +00:00
TiagoRG f0ef341c34 LSD aula01 slide moved 2023-03-01 12:18:19 +00:00
TiagoRG 665fcad3a9 LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
TiagoRG 1c107c1ca4 LSD: aula01 part1 finished 2023-03-01 12:13:35 +00:00
TiagoRG 012f4a96ea LSD material for aula02 and aula03 2023-02-25 17:54:37 +00:00
TiagoRG e4496c6c97 LSD slides added 2023-02-25 11:46:28 +00:00
TiagoRG 0369f2e282 README update 2023-02-25 11:43:18 +00:00
TiagoRG 4fbb93468b LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00