[LSD] added generic version to ALUDemo (pratica05 - part5)
This commit is contained in:
TiagoRG
parent
21266306fa
commit
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@ -20,28 +20,11 @@ refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "graphic" (version "1.4"))
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(pin
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(input)
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(rect 272 144 440 160)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "SW[7..4]" (rect 5 0 47 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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(line (pt 84 4)(pt 109 4))
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(line (pt 113 8)(pt 168 8))
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(line (pt 84 12)(pt 84 4))
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(line (pt 109 4)(pt 113 8))
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(line (pt 109 12)(pt 113 8))
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)
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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(annotation_block (location)(rect 208 160 272 176))
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)
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(pin
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(input)
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(rect 272 160 440 176)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" ))
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(text "SW[5..0]" (rect 5 0 48 13)(font "Intel Clear" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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@ -54,11 +37,28 @@ https://fpgasoftware.intel.com/eula.
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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(annotation_block (location)(rect 208 176 272 192))
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)
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(pin
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(input)
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(rect 272 144 440 160)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "SW[11..6]" (rect 5 0 54 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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(line (pt 84 4)(pt 109 4))
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(line (pt 113 8)(pt 168 8))
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(line (pt 84 12)(pt 84 4))
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(line (pt 109 4)(pt 113 8))
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(line (pt 109 12)(pt 113 8))
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)
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(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
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(annotation_block (location)(rect 208 160 272 176))
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)
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(pin
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(input)
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(rect 272 176 440 192)
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
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(text "SW[10..8]" (rect 5 0 54 11)(font "Arial" ))
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(text "SW[14..12]" (rect 5 0 61 11)(font "Arial" ))
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(pt 168 8)
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(drawing
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(line (pt 84 12)(pt 109 12))
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@ -73,9 +73,9 @@ https://fpgasoftware.intel.com/eula.
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)
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(pin
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(output)
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(rect 616 144 792 160)
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(rect 624 160 800 176)
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(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
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(text "LEDR[3..0]" (rect 90 0 144 11)(font "Arial" ))
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(text "LEDR[11..6]" (rect 90 0 150 13)(font "Intel Clear" ))
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(pt 0 8)
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(drawing
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(line (pt 0 8)(pt 52 8))
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@ -86,13 +86,13 @@ https://fpgasoftware.intel.com/eula.
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(line (pt 82 8)(pt 78 12))
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(line (pt 78 12)(pt 82 8))
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)
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(annotation_block (location)(rect 792 160 856 176))
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(annotation_block (location)(rect 800 176 856 192))
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)
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(pin
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(output)
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(rect 616 160 792 176)
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(rect 624 144 800 160)
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(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
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(text "LEDR[7..4]" (rect 90 0 143 13)(font "Intel Clear" ))
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(text "LEDR[5..0]" (rect 90 0 144 11)(font "Arial" ))
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(pt 0 8)
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(drawing
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(line (pt 0 8)(pt 52 8))
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@ -103,24 +103,24 @@ https://fpgasoftware.intel.com/eula.
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(line (pt 82 8)(pt 78 12))
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(line (pt 78 12)(pt 82 8))
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)
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(annotation_block (location)(rect 792 176 848 192))
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(annotation_block (location)(rect 800 160 864 176))
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)
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(symbol
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(rect 448 120 608 232)
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(text "ALU4" (rect 5 0 34 11)(font "Arial" ))
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(rect 448 120 616 232)
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(text "ALUN" (rect 5 0 34 11)(font "Arial" ))
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(text "inst" (rect 8 96 26 107)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "a[3..0]" (rect 0 0 30 11)(font "Arial" ))
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(text "a[3..0]" (rect 21 27 51 38)(font "Arial" ))
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(text "a[n-1..0]" (rect 0 0 41 11)(font "Arial" ))
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(text "a[n-1..0]" (rect 21 27 62 38)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "b[3..0]" (rect 0 0 30 11)(font "Arial" ))
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(text "b[3..0]" (rect 21 43 51 54)(font "Arial" ))
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(text "b[n-1..0]" (rect 0 0 41 11)(font "Arial" ))
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(text "b[n-1..0]" (rect 21 43 62 54)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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@ -131,22 +131,28 @@ https://fpgasoftware.intel.com/eula.
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(line (pt 0 64)(pt 16 64)(line_width 3))
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)
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(port
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(pt 160 32)
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(pt 168 32)
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(output)
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(text "r[3..0]" (rect 0 0 28 11)(font "Arial" ))
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(text "r[3..0]" (rect 116 27 144 38)(font "Arial" ))
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(line (pt 160 32)(pt 144 32)(line_width 3))
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(text "r[n-1..0]" (rect 0 0 38 11)(font "Arial" ))
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(text "r[n-1..0]" (rect 115 27 153 38)(font "Arial" ))
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(line (pt 168 32)(pt 152 32)(line_width 3))
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)
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(port
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(pt 160 48)
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(pt 168 48)
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(output)
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(text "m[3..0]" (rect 0 0 34 11)(font "Arial" ))
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(text "m[3..0]" (rect 111 43 145 54)(font "Arial" ))
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(line (pt 160 48)(pt 144 48)(line_width 3))
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(text "m[n-1..0]" (rect 0 0 43 11)(font "Arial" ))
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(text "m[n-1..0]" (rect 111 43 154 54)(font "Arial" ))
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(line (pt 168 48)(pt 152 48)(line_width 3))
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)
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(parameter
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"N"
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"6"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 144 96))
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(rectangle (rect 16 16 152 96))
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)
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(annotation_block (parameter)(rect 616 88 787 118))
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)
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(connector
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(pt 448 152)
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@ -164,12 +170,12 @@ https://fpgasoftware.intel.com/eula.
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(bus)
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)
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(connector
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(pt 608 152)
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(pt 616 152)
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(pt 624 152)
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(bus)
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)
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(connector
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(pt 608 168)
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(pt 616 168)
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(pt 624 168)
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(bus)
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)
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@ -0,0 +1,71 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 184 128)
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(text "ALUN" (rect 5 0 33 12)(font "Arial" ))
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(text "inst" (rect 8 96 20 108)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "a[n-1..0]" (rect 0 0 30 12)(font "Arial" ))
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(text "a[n-1..0]" (rect 21 27 51 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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(port
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(pt 0 48)
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(input)
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(text "b[n-1..0]" (rect 0 0 30 12)(font "Arial" ))
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(text "b[n-1..0]" (rect 21 43 51 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "op[2..0]" (rect 0 0 29 12)(font "Arial" ))
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(text "op[2..0]" (rect 21 59 50 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 3))
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)
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(port
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(pt 168 32)
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(output)
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(text "r[n-1..0]" (rect 0 0 29 12)(font "Arial" ))
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(text "r[n-1..0]" (rect 118 27 147 39)(font "Arial" ))
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(line (pt 168 32)(pt 152 32)(line_width 3))
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)
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(port
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(pt 168 48)
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(output)
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(text "m[n-1..0]" (rect 0 0 34 12)(font "Arial" ))
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(text "m[n-1..0]" (rect 113 43 147 55)(font "Arial" ))
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(line (pt 168 48)(pt 152 48)(line_width 3))
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)
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(parameter
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"N"
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"8"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 152 96)(line_width 1))
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)
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(annotation_block (parameter)(rect 184 -64 284 16))
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)
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@ -0,0 +1,36 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity ALUN is
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generic (N : positive := 8);
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port
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(
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a,b : in std_logic_vector((N-1) downto 0);
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op : in std_logic_vector(2 downto 0);
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r, m : out std_logic_vector((N-1) downto 0)
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);
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end ALUN;
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architecture Behavioral of ALUN is
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signal s_a, s_b, s_r : unsigned((N-1) downto 0);
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signal s_m : unsigned(((N*2)-1) downto 0);
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begin
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s_a <= unsigned(a);
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s_b <= unsigned(b);
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s_m <= s_a * s_b;
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with op select
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s_r <= s_a + s_b when "000",
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s_a - s_b when "001",
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s_m((N-1) downto 0) when "010",
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s_a / s_b when "011",
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s_a rem s_b when "100",
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s_a and s_b when "101",
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s_a or s_b when "110",
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s_a xor s_b when "111";
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r <= std_logic_vector(s_r);
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m <= std_logic_vector(s_m(((N*2)-1) downto N)) when (op = "010") else (others => '0');
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end Behavioral;
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