[LSD] 2022-2023 mini project added

This commit is contained in:
TiagoRG 2023-05-02 10:49:09 +01:00
parent 0e9913e9e9
commit 87d82c4e6d
10 changed files with 711 additions and 0 deletions

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin2Bcd is
port
(
hexIn : in std_logic_vector(3 downto 0);
decOut0 : out std_logic_vector(3 downto 0);
decOut1 : out std_logic_vector(3 downto 0)
);
end Bin2Bcd;
architecture Behavioral of Bin2Bcd is
begin
process (hexIn) is
begin
if hexIn < "1010" then
decOut0 <= hexIn;
decOut1 <= "0000";
else
if hexIn = "1010" then
decOut0 <= "0000";
elsif hexIn = "1011" then
decOut0 <= "0001";
elsif hexIn = "1100" then
decOut0 <= "0010";
elsif hexIn = "1101" then
decOut0 <= "0011";
elsif hexIn = "1110" then
decOut0 <= "0100";
else
decOut0 <= "0101";
end if;
decOut1 <= "0001";
end if;
end process;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port
(
binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0)
);
end Bin7SegDecoder;
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111001" when (binInput = "0001") else --1
"0100100" when (binInput = "0010") else --2
"0110000" when (binInput = "0011") else --3
"0011001" when (binInput = "0100") else --4
"0010010" when (binInput = "0101") else --5
"0000010" when (binInput = "0110") else --6
"1111000" when (binInput = "0111") else --7
"0000000" when (binInput = "1000") else --8
"0010000" when (binInput = "1001") else --9
"1000000"; --0
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter is
port
(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end Counter;
architecture Behavioral of Counter is
signal s_count : unsigned(3 downto 0) := to_unsigned(0, 4);
begin
process(clk, reset)
begin
if (reset = '1') then
s_count <= to_unsigned(0, 4);
elsif (start = '1' and rising_edge(clk)) then
if (std_logic_vector(s_count) = "1111") then
s_count <= to_unsigned(0, 4);
else
s_count <= s_count + 1;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterDemo is
port
(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(1 downto 0);
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0)
);
end CounterDemo;
architecture Shell of CounterDemo is
signal s_pulse, s_reset, s_toggle : std_logic;
signal s_count : std_logic_vector(3 downto 0);
signal s_startStop : std_logic := '1';
signal s_display0, s_display1 : std_logic_vector(3 downto 0);
begin
s_reset <= not KEY(1);
pulse_gen : entity work.pulse_gen(Behavioral)
generic map (MAX => 20_000_000)
port map
(
clk => CLOCK_50,
pulse => s_pulse
);
key_debounce : entity work.Debouncer(Behavioral)
port map
(
refClk => CLOCK_50,
dirtyIn => KEY(0),
pulsedOut => s_toggle
);
start_stop : entity work.ToggleSwitch(Behavioral)
port map
(
toggle => s_toggle,
reset => s_reset,
startStop => s_startStop
);
counter : entity work.Counter(Behavioral)
port map
(
clk => s_pulse,
reset => s_reset,
start => s_startStop,
count => s_count
);
bin2bcd : entity work.Bin2Bcd(Behavioral)
port map
(
hexIn => s_count,
decOut0 => s_display0,
decOut1 => s_display1
);
display0 : entity work.Bin7SegDecoder(Behavioral)
port map
(
binInput => s_display0,
decOut_n => HEX0
);
display1 : entity work.Bin7SegDecoder(Behavioral)
port map
(
binInput => s_display1,
decOut_n => HEX1
);
end Shell;

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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/projects/MiniProj_Demo_22-23/CounterSimulation.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/projects/MiniProj_Demo_22-23/simulation/qsim/CounterSimulation.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/projects/MiniProj_Demo_22-23/CounterSimulation.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/projects/MiniProj_Demo_22-23/simulation/qsim/CounterSimulation.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/projects/MiniProj_Demo_22-23/simulation/qsim/" CounterDemo -c CounterDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/projects/MiniProj_Demo_22-23/simulation/qsim/" CounterDemo -c CounterDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work CounterDemo.vho
vcom -work work CounterSimulation.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDemo_vhd_vec_tst
vcd file -direction CounterDemo.msim.vcd
vcd add -internal CounterDemo_vhd_vec_tst/*
vcd add -internal CounterDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work CounterDemo.vho
vcom -work work CounterSimulation.vwf.vht
vsim -novopt -c -t 1ps -sdfmax CounterDemo_vhd_vec_tst/i1=CounterDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDemo_vhd_vec_tst
vcd file -direction CounterDemo.msim.vcd
vcd add -internal CounterDemo_vhd_vec_tst/*
vcd add -internal CounterDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("count")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("count[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("reset")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("start")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
TRANSITION_LIST("count[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("reset")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 910.0;
}
}
TRANSITION_LIST("start")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "reset";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "start";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "count";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
CHILDREN = 4, 5, 6, 7;
}
DISPLAY_LINE
{
CHANNEL = "count[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "count[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "count[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "count[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 3;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Debouncer is
generic( kHzClkFreq : positive := 50_000;
mSecMinInWidth : positive := 100;
inPolarity : std_logic := '0';
outPolarity : std_logic := '1');
port( refClk : in std_logic;
dirtyIn : in std_logic;
pulsedOut : out std_logic);
end Debouncer;
architecture Behavioral of Debouncer is
constant MIN_IN_WIDTH_CYCLES : positive := mSecMinInWidth * kHzClkFreq;
subtype TCounter is natural range 0 to MIN_IN_WIDTH_CYCLES;
signal s_debounceCnt : TCounter := 0;
signal s_dirtyIn, s_previousIn, s_pulsedOut : std_logic;
begin
in_sync_proc : process(refClk)
begin
if (rising_edge(refClk)) then
if (inPolarity = '1') then
s_dirtyIn <= dirtyIn;
else
s_dirtyIn <= not dirtyIn;
end if;
s_previousIn <= s_dirtyIn;
end if;
end process;
count_proc : process(refClk)
begin
if (rising_edge(refClk)) then
if ((s_dirtyIn = '0') or
(s_debounceCnt > MIN_IN_WIDTH_CYCLES)) then
s_debounceCnt <= 0;
s_pulsedOut <= '0';
elsif (s_dirtyIn = '1') then
if (s_previousIn = '0') then
s_debounceCnt <= MIN_IN_WIDTH_CYCLES;
s_pulsedOut <= '0';
else
if (s_debounceCnt >= 1) then
s_debounceCnt <= s_debounceCnt - 1;
end if;
if (s_debounceCnt = 1) then
s_pulsedOut <= '1';
else
s_pulsedOut <= '0';
end if;
end if;
end if;
end if;
end process;
pulsedOut <= s_pulsedOut when (outPolarity = '1') else not s_pulsedOut;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ToggleSwitch is
port
(
toggle : in std_logic;
reset : in std_logic;
startStop : out std_logic := '1'
);
end ToggleSwitch;
architecture Behavioral of ToggleSwitch is
signal current_state : std_logic := '1';
begin
process(toggle, reset)
begin
if (reset = '1') then
current_state <= '1';
else
if (toggle = '1') then
if (current_state = '1') then
current_state <= '0';
else
current_state <= '1';
end if;
end if;
end if;
end process;
startStop <= current_state;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pulse_gen is
generic (MAX : positive := 50_000_000);
port
(
clk : in STD_LOGIC;
pulse : out STD_LOGIC
);
end pulse_gen;
architecture Behavioral of pulse_gen is
signal s_cnt : natural range 0 to MAX-1;
begin
process(clk)
begin
if (rising_edge(clk)) then
pulse <= '0';
s_cnt <= s_cnt + 1;
if (s_cnt = MAX-1) then
s_cnt <= 0;
pulse <= '1';
end if;
end if;
end process;
end Behavioral;

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<internal_error>
<sub_system>ERR</sub_system>
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0x7f1ace73ec2b: jtag_client + 0x82c2b (__cxa_throw + 0x5b)
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0x7f1ab18b96fc: QtGui.so.4 + 0x6b96fc (_ZN13QMdiSubWindow10closeEventEP11QCloseEvent + 0xcc)
0x7f1acf2a88cf: sys_qui + 0xb28cf (_ZN15QUI_MDI_SUB_WND10closeEventEP11QCloseEvent + 0x567)
0x7f1ab14668aa: QtGui.so.4 + 0x2668aa (_ZN7QWidget5eventEP6QEvent + 0xdea)
0x7f1ab18b996b: QtGui.so.4 + 0x6b996b (_ZN13QMdiSubWindow5eventEP6QEvent + 0x18b)
0x7f1ab140484f: QtGui.so.4 + 0x20484f (_ZN19QApplicationPrivate13notify_helperEP7QObjectP6QEvent + 0xaf)
0x7f1ab140aea3: QtGui.so.4 + 0x20aea3 (_ZN12QApplication6notifyEP7QObjectP6QEvent + 0x183)
0x7f1ac9db5ac4: QtCore.so.4 + 0x1b5ac4 (_ZN16QCoreApplication14notifyInternalEP7QObjectP6QEvent + 0x84)
0x7f1ab145d3f8: QtGui.so.4 + 0x25d3f8 (_ZN14QWidgetPrivate12close_helperENS_9CloseModeE + 0x1f8)
0x7f1ab145d4e2: QtGui.so.4 + 0x25d4e2 (_ZN7QWidget5closeEv + 0x12)
0x7f1acf28c00a: sys_qui + 0x9600a (_ZN13QUI_FRAME_WND17close_all_in_listE5QListIP13QMdiSubWindowES2_5_GUID + 0x374)
0x7f1acf28c137: sys_qui + 0x96137 (_ZN13QUI_FRAME_WND17close_all_windowsE5_GUID + 0xed)
0x7f1acf29b269: sys_qui + 0xa5269 (_ZN13QUI_FRAME_WND10closeEventEP11QCloseEvent + 0x25f)
0x7f1acf3f5aa9: sys_qgq + 0x19aa9 (_ZN15QGQ_MAIN_WINDOW10closeEventEP11QCloseEvent + 0x35)
0x7f1ab14668aa: QtGui.so.4 + 0x2668aa (_ZN7QWidget5eventEP6QEvent + 0xdea)
0x7f1ab189995c: QtGui.so.4 + 0x69995c (_ZN11QMainWindow5eventEP6QEvent + 0x13c)
0x7f1ab140484f: QtGui.so.4 + 0x20484f (_ZN19QApplicationPrivate13notify_helperEP7QObjectP6QEvent + 0xaf)
0x7f1ab140aea3: QtGui.so.4 + 0x20aea3 (_ZN12QApplication6notifyEP7QObjectP6QEvent + 0x183)
0x7f1ac9db5ac4: QtCore.so.4 + 0x1b5ac4 (_ZN16QCoreApplication14notifyInternalEP7QObjectP6QEvent + 0x84)
0x7f1ab145d3f8: QtGui.so.4 + 0x25d3f8 (_ZN14QWidgetPrivate12close_helperENS_9CloseModeE + 0x1f8)
0x7f1ab147e882: QtGui.so.4 + 0x27e882
0x7f1ab1480fa5: QtGui.so.4 + 0x280fa5 (_ZN12QApplication16x11ClientMessageEP7QWidgetP7_XEventb + 0x1e5)
0x7f1ab148d7a1: QtGui.so.4 + 0x28d7a1 (_ZN12QApplication15x11ProcessEventEP7_XEvent + 0xfa1)
0x7f1ab14b8d62: QtGui.so.4 + 0x2b8d62
0x7f1ab631bd3b: glib-2.0.so.0 + 0x55d3b (g_main_context_dispatch + 0x26b)
0x7f1ab63706c8: glib-2.0.so.0 + 0xaa6c8
0x7f1ab63193e3: glib-2.0.so.0 + 0x533e3 (g_main_context_iteration + 0x33)
0x7f1ac9de8af5: QtCore.so.4 + 0x1e8af5 (_ZN20QEventDispatcherGlib13processEventsE6QFlagsIN10QEventLoop17ProcessEventsFlagEE + 0x65)
0x7f1ab14b889f: QtGui.so.4 + 0x2b889f
0x7f1ac9db4ad5: QtCore.so.4 + 0x1b4ad5 (_ZN10QEventLoop13processEventsE6QFlagsINS_17ProcessEventsFlagEE + 0x35)
0x7f1ac9db4ea8: QtCore.so.4 + 0x1b4ea8 (_ZN10QEventLoop4execE6QFlagsINS_17ProcessEventsFlagEE + 0x128)
0x7f1ac9db9cc4: QtCore.so.4 + 0x1b9cc4 (_ZN16QCoreApplication4execEv + 0xb4)
0x401eab: quartus + 0x1eab (_Z8qgq_mainiPPKc + 0x7b)
0x7f1abf14fe30: ccl_msg + 0x3ee30 (_Z15msg_main_threadPv + 0x10)
0x7f1abe181acc: ccl_thr + 0x5acc (thr_final_wrapper + 0xc)
0x7f1abf14feef: ccl_msg + 0x3eeef (_Z18msg_thread_wrapperPFPvS_ES_ + 0x62)
0x7f1abe1e9f9c: ccl_mem + 0x9f9c (_Z18mem_thread_wrapperPFPvS_ES_ + 0x5c)
0x7f1abe1b8b39: ccl_err + 0x8b39 (_Z18err_thread_wrapperPFPvS_ES_ + 0x27)
0x7f1abe181b0f: ccl_thr + 0x5b0f (thr_thread_wrapper + 0x15)
0x7f1abf151ea1: ccl_msg + 0x40ea1 (_Z12msg_exe_mainiPPKcPFiiS1_E + 0xb2)
</callstack>
<error>*** Fatal Error: Unhandled Exception</error>
<date>Tue May 2 10:47:59 2023
</date>
<version>Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition</version>
</internal_error>