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[ISD] MuxDemo update

This commit is contained in:
TiagoRG 2023-03-09 17:44:51 +00:00
parent 1ccf4d9f06
commit 557dc6e208
52 changed files with 2475 additions and 1314 deletions
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177
1ano/1semestre/isd/quartus-projects/MuxDemo/Mux16_1.bsf Normal file
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@ -0,0 +1,177 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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597
1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
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Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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(input)
(text "I14" (rect 0 0 20 15)(font "Intel Clear" (font_size 8)))
(text "I14" (rect 21 315 41 330)(font "Intel Clear" (font_size 8)))
(line (pt 0 320)(pt 16 320))
)
(port
(pt 0 336)
(input)
(text "I15" (rect 0 0 20 15)(font "Intel Clear" (font_size 8)))
(text "I15" (rect 21 331 41 346)(font "Intel Clear" (font_size 8)))
(line (pt 0 336)(pt 16 336))
)
(port
(pt 96 32)
(output)
(text "Y" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "Y" (rect 66 27 75 42)(font "Intel Clear" (font_size 8)))
(line (pt 96 32)(pt 80 32))
)
(drawing
(rectangle (rect 16 16 80 368))
)
)
(connector
(pt 488 152)
(pt 480 152)
)
(connector
(pt 488 200)
(pt 480 200)
)
(connector
(pt 488 216)
(pt 480 216)
)
(connector
(pt 488 232)
(pt 480 232)
)
(connector
(pt 488 248)
(pt 480 248)
)
(connector
(pt 488 264)
(pt 480 264)
)
(connector
(pt 488 280)
(pt 480 280)
)
(connector
(pt 488 296)
(pt 480 296)
)
(connector
(pt 488 312)
(pt 480 312)
)
(connector
(pt 488 328)
(pt 480 328)
)
(connector
(pt 488 344)
(pt 480 344)
)
(connector
(pt 488 360)
(pt 480 360)
)
(connector
(pt 488 376)
(pt 480 376)
)
(connector
(pt 488 392)
(pt 480 392)
)
(connector
(pt 488 408)
(pt 480 408)
)
(connector
(pt 488 168)
(pt 480 168)
)
(connector
(pt 488 184)
(pt 480 184)
)
(connector
(pt 488 104)
(pt 480 104)
)
(connector
(pt 488 120)
(pt 480 120)
)
(connector
(pt 488 136)
(pt 480 136)
)
(connector
(pt 584 104)
(pt 592 104)
)

528
1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.qsf
View File

@ -39,7 +39,7 @@
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE auto set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY Mux16_1 set_global_assignment -name TOP_LEVEL_ENTITY MuxDemo
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:24:51 NOVEMBER 18, 2022" set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:24:51 NOVEMBER 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
@ -52,9 +52,529 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name BDF_FILE Mux16_1.bdf set_global_assignment -name BDF_FILE Mux16_1.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Mux16_1.vwf
set_global_assignment -name BDF_FILE MuxDemo.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_location_assignment PIN_Y2 -to CLOCK_50
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_location_assignment PIN_AG14 -to CLOCK2_50
set_global_assignment -name VECTOR_WAVEFORM_FILE Mux16_1.vwf set_location_assignment PIN_AG15 -to CLOCK3_50
set_location_assignment PIN_AH14 -to SMA_CLKIN
set_location_assignment PIN_AE23 -to SMA_CLKOUT
set_location_assignment PIN_M23 -to KEY[0]
set_location_assignment PIN_M21 -to KEY[1]
set_location_assignment PIN_N21 -to KEY[2]
set_location_assignment PIN_R24 -to KEY[3]
set_location_assignment PIN_AB28 -to SW[0]
set_location_assignment PIN_AC28 -to SW[1]
set_location_assignment PIN_AC27 -to SW[2]
set_location_assignment PIN_AD27 -to SW[3]
set_location_assignment PIN_AB27 -to SW[4]
set_location_assignment PIN_AC26 -to SW[5]
set_location_assignment PIN_AD26 -to SW[6]
set_location_assignment PIN_AB26 -to SW[7]
set_location_assignment PIN_AC25 -to SW[8]
set_location_assignment PIN_AB25 -to SW[9]
set_location_assignment PIN_AC24 -to SW[10]
set_location_assignment PIN_AB24 -to SW[11]
set_location_assignment PIN_AB23 -to SW[12]
set_location_assignment PIN_AA24 -to SW[13]
set_location_assignment PIN_AA23 -to SW[14]
set_location_assignment PIN_AA22 -to SW[15]
set_location_assignment PIN_Y24 -to SW[16]
set_location_assignment PIN_Y23 -to SW[17]
set_location_assignment PIN_G19 -to LEDR[0]
set_location_assignment PIN_F19 -to LEDR[1]
set_location_assignment PIN_E19 -to LEDR[2]
set_location_assignment PIN_F21 -to LEDR[3]
set_location_assignment PIN_F18 -to LEDR[4]
set_location_assignment PIN_E18 -to LEDR[5]
set_location_assignment PIN_J19 -to LEDR[6]
set_location_assignment PIN_H19 -to LEDR[7]
set_location_assignment PIN_J17 -to LEDR[8]
set_location_assignment PIN_G17 -to LEDR[9]
set_location_assignment PIN_J15 -to LEDR[10]
set_location_assignment PIN_H16 -to LEDR[11]
set_location_assignment PIN_J16 -to LEDR[12]
set_location_assignment PIN_H17 -to LEDR[13]
set_location_assignment PIN_F15 -to LEDR[14]
set_location_assignment PIN_G15 -to LEDR[15]
set_location_assignment PIN_G16 -to LEDR[16]
set_location_assignment PIN_H15 -to LEDR[17]
set_location_assignment PIN_E21 -to LEDG[0]
set_location_assignment PIN_E22 -to LEDG[1]
set_location_assignment PIN_E25 -to LEDG[2]
set_location_assignment PIN_E24 -to LEDG[3]
set_location_assignment PIN_H21 -to LEDG[4]
set_location_assignment PIN_G20 -to LEDG[5]
set_location_assignment PIN_G22 -to LEDG[6]
set_location_assignment PIN_G21 -to LEDG[7]
set_location_assignment PIN_F17 -to LEDG[8]
set_location_assignment PIN_G18 -to HEX0[0]
set_location_assignment PIN_F22 -to HEX0[1]
set_location_assignment PIN_E17 -to HEX0[2]
set_location_assignment PIN_L26 -to HEX0[3]
set_location_assignment PIN_L25 -to HEX0[4]
set_location_assignment PIN_J22 -to HEX0[5]
set_location_assignment PIN_H22 -to HEX0[6]
set_location_assignment PIN_M24 -to HEX1[0]
set_location_assignment PIN_Y22 -to HEX1[1]
set_location_assignment PIN_W21 -to HEX1[2]
set_location_assignment PIN_W22 -to HEX1[3]
set_location_assignment PIN_W25 -to HEX1[4]
set_location_assignment PIN_U23 -to HEX1[5]
set_location_assignment PIN_U24 -to HEX1[6]
set_location_assignment PIN_AA25 -to HEX2[0]
set_location_assignment PIN_AA26 -to HEX2[1]
set_location_assignment PIN_Y25 -to HEX2[2]
set_location_assignment PIN_W26 -to HEX2[3]
set_location_assignment PIN_Y26 -to HEX2[4]
set_location_assignment PIN_W27 -to HEX2[5]
set_location_assignment PIN_W28 -to HEX2[6]
set_location_assignment PIN_V21 -to HEX3[0]
set_location_assignment PIN_U21 -to HEX3[1]
set_location_assignment PIN_AB20 -to HEX3[2]
set_location_assignment PIN_AA21 -to HEX3[3]
set_location_assignment PIN_AD24 -to HEX3[4]
set_location_assignment PIN_AF23 -to HEX3[5]
set_location_assignment PIN_Y19 -to HEX3[6]
set_location_assignment PIN_AB19 -to HEX4[0]
set_location_assignment PIN_AA19 -to HEX4[1]
set_location_assignment PIN_AG21 -to HEX4[2]
set_location_assignment PIN_AH21 -to HEX4[3]
set_location_assignment PIN_AE19 -to HEX4[4]
set_location_assignment PIN_AF19 -to HEX4[5]
set_location_assignment PIN_AE18 -to HEX4[6]
set_location_assignment PIN_AD18 -to HEX5[0]
set_location_assignment PIN_AC18 -to HEX5[1]
set_location_assignment PIN_AB18 -to HEX5[2]
set_location_assignment PIN_AH19 -to HEX5[3]
set_location_assignment PIN_AG19 -to HEX5[4]
set_location_assignment PIN_AF18 -to HEX5[5]
set_location_assignment PIN_AH18 -to HEX5[6]
set_location_assignment PIN_AA17 -to HEX6[0]
set_location_assignment PIN_AB16 -to HEX6[1]
set_location_assignment PIN_AA16 -to HEX6[2]
set_location_assignment PIN_AB17 -to HEX6[3]
set_location_assignment PIN_AB15 -to HEX6[4]
set_location_assignment PIN_AA15 -to HEX6[5]
set_location_assignment PIN_AC17 -to HEX6[6]
set_location_assignment PIN_AD17 -to HEX7[0]
set_location_assignment PIN_AE17 -to HEX7[1]
set_location_assignment PIN_AG17 -to HEX7[2]
set_location_assignment PIN_AH17 -to HEX7[3]
set_location_assignment PIN_AF17 -to HEX7[4]
set_location_assignment PIN_AG18 -to HEX7[5]
set_location_assignment PIN_AA14 -to HEX7[6]
set_location_assignment PIN_L3 -to LCD_DATA[0]
set_location_assignment PIN_L1 -to LCD_DATA[1]
set_location_assignment PIN_L2 -to LCD_DATA[2]
set_location_assignment PIN_K7 -to LCD_DATA[3]
set_location_assignment PIN_K1 -to LCD_DATA[4]
set_location_assignment PIN_K2 -to LCD_DATA[5]
set_location_assignment PIN_M3 -to LCD_DATA[6]
set_location_assignment PIN_M5 -to LCD_DATA[7]
set_location_assignment PIN_L6 -to LCD_BLON
set_location_assignment PIN_M1 -to LCD_RW
set_location_assignment PIN_L4 -to LCD_EN
set_location_assignment PIN_M2 -to LCD_RS
set_location_assignment PIN_L5 -to LCD_ON
set_location_assignment PIN_G9 -to UART_TXD
set_location_assignment PIN_G12 -to UART_RXD
set_location_assignment PIN_G14 -to UART_CTS
set_location_assignment PIN_J13 -to UART_RTS
set_location_assignment PIN_G6 -to PS2_CLK
set_location_assignment PIN_H5 -to PS2_DAT
set_location_assignment PIN_G5 -to PS2_CLK2
set_location_assignment PIN_F5 -to PS2_DAT2
set_location_assignment PIN_AE13 -to SD_CLK
set_location_assignment PIN_AD14 -to SD_CMD
set_location_assignment PIN_AF14 -to SD_WP_N
set_location_assignment PIN_AE14 -to SD_DAT[0]
set_location_assignment PIN_AF13 -to SD_DAT[1]
set_location_assignment PIN_AB14 -to SD_DAT[2]
set_location_assignment PIN_AC14 -to SD_DAT[3]
set_location_assignment PIN_G13 -to VGA_HS
set_location_assignment PIN_C13 -to VGA_VS
set_location_assignment PIN_C10 -to VGA_SYNC_N
set_location_assignment PIN_A12 -to VGA_CLK
set_location_assignment PIN_F11 -to VGA_BLANK_N
set_location_assignment PIN_E12 -to VGA_R[0]
set_location_assignment PIN_E11 -to VGA_R[1]
set_location_assignment PIN_D10 -to VGA_R[2]
set_location_assignment PIN_F12 -to VGA_R[3]
set_location_assignment PIN_G10 -to VGA_R[4]
set_location_assignment PIN_J12 -to VGA_R[5]
set_location_assignment PIN_H8 -to VGA_R[6]
set_location_assignment PIN_H10 -to VGA_R[7]
set_location_assignment PIN_G8 -to VGA_G[0]
set_location_assignment PIN_G11 -to VGA_G[1]
set_location_assignment PIN_F8 -to VGA_G[2]
set_location_assignment PIN_H12 -to VGA_G[3]
set_location_assignment PIN_C8 -to VGA_G[4]
set_location_assignment PIN_B8 -to VGA_G[5]
set_location_assignment PIN_F10 -to VGA_G[6]
set_location_assignment PIN_C9 -to VGA_G[7]
set_location_assignment PIN_B10 -to VGA_B[0]
set_location_assignment PIN_A10 -to VGA_B[1]
set_location_assignment PIN_C11 -to VGA_B[2]
set_location_assignment PIN_B11 -to VGA_B[3]
set_location_assignment PIN_A11 -to VGA_B[4]
set_location_assignment PIN_C12 -to VGA_B[5]
set_location_assignment PIN_D11 -to VGA_B[6]
set_location_assignment PIN_D12 -to VGA_B[7]
set_location_assignment PIN_C2 -to AUD_ADCLRCK
set_location_assignment PIN_D2 -to AUD_ADCDAT
set_location_assignment PIN_E3 -to AUD_DACLRCK
set_location_assignment PIN_D1 -to AUD_DACDAT
set_location_assignment PIN_E1 -to AUD_XCK
set_location_assignment PIN_F2 -to AUD_BCLK
set_location_assignment PIN_D14 -to EEP_I2C_SCLK
set_location_assignment PIN_E14 -to EEP_I2C_SDAT
set_location_assignment PIN_B7 -to I2C_SCLK
set_location_assignment PIN_A8 -to I2C_SDAT
set_location_assignment PIN_A14 -to ENETCLK_25
set_location_assignment PIN_C14 -to ENET0_LINK100
set_location_assignment PIN_A17 -to ENET0_GTX_CLK
set_location_assignment PIN_C19 -to ENET0_RST_N
set_location_assignment PIN_C20 -to ENET0_MDC
set_location_assignment PIN_B21 -to ENET0_MDIO
set_location_assignment PIN_A21 -to ENET0_INT_N
set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
set_location_assignment PIN_B17 -to ENET0_TX_CLK
set_location_assignment PIN_A18 -to ENET0_TX_EN
set_location_assignment PIN_B18 -to ENET0_TX_ER
set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
set_location_assignment PIN_A15 -to ENET0_RX_CLK
set_location_assignment PIN_C17 -to ENET0_RX_DV
set_location_assignment PIN_D18 -to ENET0_RX_ER
set_location_assignment PIN_D15 -to ENET0_RX_CRS
set_location_assignment PIN_E15 -to ENET0_RX_COL
set_location_assignment PIN_D13 -to ENET1_LINK100
set_location_assignment PIN_C23 -to ENET1_GTX_CLK
set_location_assignment PIN_D22 -to ENET1_RST_N
set_location_assignment PIN_D23 -to ENET1_MDC
set_location_assignment PIN_D25 -to ENET1_MDIO
set_location_assignment PIN_D24 -to ENET1_INT_N
set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
set_location_assignment PIN_C22 -to ENET1_TX_CLK
set_location_assignment PIN_B25 -to ENET1_TX_EN
set_location_assignment PIN_A25 -to ENET1_TX_ER
set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
set_location_assignment PIN_B15 -to ENET1_RX_CLK
set_location_assignment PIN_A22 -to ENET1_RX_DV
set_location_assignment PIN_C24 -to ENET1_RX_ER
set_location_assignment PIN_D20 -to ENET1_RX_CRS
set_location_assignment PIN_B22 -to ENET1_RX_COL
set_location_assignment PIN_E5 -to TD_HS
set_location_assignment PIN_E4 -to TD_VS
set_location_assignment PIN_B14 -to TD_CLK27
set_location_assignment PIN_G7 -to TD_RESET_N
set_location_assignment PIN_E8 -to TD_DATA[0]
set_location_assignment PIN_A7 -to TD_DATA[1]
set_location_assignment PIN_D8 -to TD_DATA[2]
set_location_assignment PIN_C7 -to TD_DATA[3]
set_location_assignment PIN_D7 -to TD_DATA[4]
set_location_assignment PIN_D6 -to TD_DATA[5]
set_location_assignment PIN_E7 -to TD_DATA[6]
set_location_assignment PIN_F7 -to TD_DATA[7]
set_location_assignment PIN_J6 -to OTG_DATA[0]
set_location_assignment PIN_K4 -to OTG_DATA[1]
set_location_assignment PIN_J5 -to OTG_DATA[2]
set_location_assignment PIN_K3 -to OTG_DATA[3]
set_location_assignment PIN_J4 -to OTG_DATA[4]
set_location_assignment PIN_J3 -to OTG_DATA[5]
set_location_assignment PIN_J7 -to OTG_DATA[6]
set_location_assignment PIN_H6 -to OTG_DATA[7]
set_location_assignment PIN_H3 -to OTG_DATA[8]
set_location_assignment PIN_H4 -to OTG_DATA[9]
set_location_assignment PIN_G1 -to OTG_DATA[10]
set_location_assignment PIN_G2 -to OTG_DATA[11]
set_location_assignment PIN_G3 -to OTG_DATA[12]
set_location_assignment PIN_F1 -to OTG_DATA[13]
set_location_assignment PIN_F3 -to OTG_DATA[14]
set_location_assignment PIN_G4 -to OTG_DATA[15]
set_location_assignment PIN_H7 -to OTG_ADDR[0]
set_location_assignment PIN_C3 -to OTG_ADDR[1]
set_location_assignment PIN_J1 -to OTG_DREQ[0]
set_location_assignment PIN_A3 -to OTG_CS_N
set_location_assignment PIN_A4 -to OTG_WR_N
set_location_assignment PIN_B3 -to OTG_RD_N
set_location_assignment PIN_D5 -to OTG_INT
set_location_assignment PIN_C5 -to OTG_RST_N
set_location_assignment PIN_Y15 -to IRDA_RXD
set_location_assignment PIN_U7 -to DRAM_BA[0]
set_location_assignment PIN_R4 -to DRAM_BA[1]
set_location_assignment PIN_U2 -to DRAM_DQM[0]
set_location_assignment PIN_W4 -to DRAM_DQM[1]
set_location_assignment PIN_K8 -to DRAM_DQM[2]
set_location_assignment PIN_N8 -to DRAM_DQM[3]
set_location_assignment PIN_U6 -to DRAM_RAS_N
set_location_assignment PIN_V7 -to DRAM_CAS_N
set_location_assignment PIN_AA6 -to DRAM_CKE
set_location_assignment PIN_AE5 -to DRAM_CLK
set_location_assignment PIN_V6 -to DRAM_WE_N
set_location_assignment PIN_T4 -to DRAM_CS_N
set_location_assignment PIN_W3 -to DRAM_DQ[0]
set_location_assignment PIN_W2 -to DRAM_DQ[1]
set_location_assignment PIN_V4 -to DRAM_DQ[2]
set_location_assignment PIN_W1 -to DRAM_DQ[3]
set_location_assignment PIN_V3 -to DRAM_DQ[4]
set_location_assignment PIN_V2 -to DRAM_DQ[5]
set_location_assignment PIN_V1 -to DRAM_DQ[6]
set_location_assignment PIN_U3 -to DRAM_DQ[7]
set_location_assignment PIN_Y3 -to DRAM_DQ[8]
set_location_assignment PIN_Y4 -to DRAM_DQ[9]
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
set_location_assignment PIN_AA3 -to DRAM_DQ[11]
set_location_assignment PIN_AB2 -to DRAM_DQ[12]
set_location_assignment PIN_AC1 -to DRAM_DQ[13]
set_location_assignment PIN_AB3 -to DRAM_DQ[14]
set_location_assignment PIN_AC2 -to DRAM_DQ[15]
set_location_assignment PIN_M8 -to DRAM_DQ[16]
set_location_assignment PIN_L8 -to DRAM_DQ[17]
set_location_assignment PIN_P2 -to DRAM_DQ[18]
set_location_assignment PIN_N3 -to DRAM_DQ[19]
set_location_assignment PIN_N4 -to DRAM_DQ[20]
set_location_assignment PIN_M4 -to DRAM_DQ[21]
set_location_assignment PIN_M7 -to DRAM_DQ[22]
set_location_assignment PIN_L7 -to DRAM_DQ[23]
set_location_assignment PIN_U5 -to DRAM_DQ[24]
set_location_assignment PIN_R7 -to DRAM_DQ[25]
set_location_assignment PIN_R1 -to DRAM_DQ[26]
set_location_assignment PIN_R2 -to DRAM_DQ[27]
set_location_assignment PIN_R3 -to DRAM_DQ[28]
set_location_assignment PIN_T3 -to DRAM_DQ[29]
set_location_assignment PIN_U4 -to DRAM_DQ[30]
set_location_assignment PIN_U1 -to DRAM_DQ[31]
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
set_location_assignment PIN_V8 -to DRAM_ADDR[1]
set_location_assignment PIN_U8 -to DRAM_ADDR[2]
set_location_assignment PIN_P1 -to DRAM_ADDR[3]
set_location_assignment PIN_V5 -to DRAM_ADDR[4]
set_location_assignment PIN_W8 -to DRAM_ADDR[5]
set_location_assignment PIN_W7 -to DRAM_ADDR[6]
set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
set_location_assignment PIN_R5 -to DRAM_ADDR[10]
set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
set_location_assignment PIN_T7 -to SRAM_ADDR[9]
set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
set_location_assignment PIN_T8 -to SRAM_ADDR[19]
set_location_assignment PIN_AH3 -to SRAM_DQ[0]
set_location_assignment PIN_AF4 -to SRAM_DQ[1]
set_location_assignment PIN_AG4 -to SRAM_DQ[2]
set_location_assignment PIN_AH4 -to SRAM_DQ[3]
set_location_assignment PIN_AF6 -to SRAM_DQ[4]
set_location_assignment PIN_AG6 -to SRAM_DQ[5]
set_location_assignment PIN_AH6 -to SRAM_DQ[6]
set_location_assignment PIN_AF7 -to SRAM_DQ[7]
set_location_assignment PIN_AD1 -to SRAM_DQ[8]
set_location_assignment PIN_AD2 -to SRAM_DQ[9]
set_location_assignment PIN_AE2 -to SRAM_DQ[10]
set_location_assignment PIN_AE1 -to SRAM_DQ[11]
set_location_assignment PIN_AE3 -to SRAM_DQ[12]
set_location_assignment PIN_AE4 -to SRAM_DQ[13]
set_location_assignment PIN_AF3 -to SRAM_DQ[14]
set_location_assignment PIN_AG3 -to SRAM_DQ[15]
set_location_assignment PIN_AC4 -to SRAM_UB_N
set_location_assignment PIN_AD4 -to SRAM_LB_N
set_location_assignment PIN_AF8 -to SRAM_CE_N
set_location_assignment PIN_AD5 -to SRAM_OE_N
set_location_assignment PIN_AE8 -to SRAM_WE_N
set_location_assignment PIN_AG12 -to FL_ADDR[0]
set_location_assignment PIN_AH7 -to FL_ADDR[1]
set_location_assignment PIN_Y13 -to FL_ADDR[2]
set_location_assignment PIN_Y14 -to FL_ADDR[3]
set_location_assignment PIN_Y12 -to FL_ADDR[4]
set_location_assignment PIN_AA13 -to FL_ADDR[5]
set_location_assignment PIN_AA12 -to FL_ADDR[6]
set_location_assignment PIN_AB13 -to FL_ADDR[7]
set_location_assignment PIN_AB12 -to FL_ADDR[8]
set_location_assignment PIN_AB10 -to FL_ADDR[9]
set_location_assignment PIN_AE9 -to FL_ADDR[10]
set_location_assignment PIN_AF9 -to FL_ADDR[11]
set_location_assignment PIN_AA10 -to FL_ADDR[12]
set_location_assignment PIN_AD8 -to FL_ADDR[13]
set_location_assignment PIN_AC8 -to FL_ADDR[14]
set_location_assignment PIN_Y10 -to FL_ADDR[15]
set_location_assignment PIN_AA8 -to FL_ADDR[16]
set_location_assignment PIN_AH12 -to FL_ADDR[17]
set_location_assignment PIN_AC12 -to FL_ADDR[18]
set_location_assignment PIN_AD12 -to FL_ADDR[19]
set_location_assignment PIN_AE10 -to FL_ADDR[20]
set_location_assignment PIN_AD10 -to FL_ADDR[21]
set_location_assignment PIN_AD11 -to FL_ADDR[22]
set_location_assignment PIN_AH8 -to FL_DQ[0]
set_location_assignment PIN_AF10 -to FL_DQ[1]
set_location_assignment PIN_AG10 -to FL_DQ[2]
set_location_assignment PIN_AH10 -to FL_DQ[3]
set_location_assignment PIN_AF11 -to FL_DQ[4]
set_location_assignment PIN_AG11 -to FL_DQ[5]
set_location_assignment PIN_AH11 -to FL_DQ[6]
set_location_assignment PIN_AF12 -to FL_DQ[7]
set_location_assignment PIN_AG7 -to FL_CE_N
set_location_assignment PIN_AG8 -to FL_OE_N
set_location_assignment PIN_AE11 -to FL_RST_N
set_location_assignment PIN_Y1 -to FL_RY
set_location_assignment PIN_AC10 -to FL_WE_N
set_location_assignment PIN_AE12 -to FL_WP_N
set_location_assignment PIN_AB22 -to GPIO[0]
set_location_assignment PIN_AC15 -to GPIO[1]
set_location_assignment PIN_AB21 -to GPIO[2]
set_location_assignment PIN_Y17 -to GPIO[3]
set_location_assignment PIN_AC21 -to GPIO[4]
set_location_assignment PIN_Y16 -to GPIO[5]
set_location_assignment PIN_AD21 -to GPIO[6]
set_location_assignment PIN_AE16 -to GPIO[7]
set_location_assignment PIN_AD15 -to GPIO[8]
set_location_assignment PIN_AE15 -to GPIO[9]
set_location_assignment PIN_AC19 -to GPIO[10]
set_location_assignment PIN_AF16 -to GPIO[11]
set_location_assignment PIN_AD19 -to GPIO[12]
set_location_assignment PIN_AF15 -to GPIO[13]
set_location_assignment PIN_AF24 -to GPIO[14]
set_location_assignment PIN_AE21 -to GPIO[15]
set_location_assignment PIN_AF25 -to GPIO[16]
set_location_assignment PIN_AC22 -to GPIO[17]
set_location_assignment PIN_AE22 -to GPIO[18]
set_location_assignment PIN_AF21 -to GPIO[19]
set_location_assignment PIN_AF22 -to GPIO[20]
set_location_assignment PIN_AD22 -to GPIO[21]
set_location_assignment PIN_AG25 -to GPIO[22]
set_location_assignment PIN_AD25 -to GPIO[23]
set_location_assignment PIN_AH25 -to GPIO[24]
set_location_assignment PIN_AE25 -to GPIO[25]
set_location_assignment PIN_AG22 -to GPIO[26]
set_location_assignment PIN_AE24 -to GPIO[27]
set_location_assignment PIN_AH22 -to GPIO[28]
set_location_assignment PIN_AF26 -to GPIO[29]
set_location_assignment PIN_AE20 -to GPIO[30]
set_location_assignment PIN_AG23 -to GPIO[31]
set_location_assignment PIN_AF20 -to GPIO[32]
set_location_assignment PIN_AH26 -to GPIO[33]
set_location_assignment PIN_AH23 -to GPIO[34]
set_location_assignment PIN_AG26 -to GPIO[35]
set_location_assignment PIN_AH15 -to HSMC_CLKIN0
set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
set_location_assignment PIN_AE26 -to HSMC_D[0]
set_location_assignment PIN_AE28 -to HSMC_D[1]
set_location_assignment PIN_AE27 -to HSMC_D[2]
set_location_assignment PIN_AF27 -to HSMC_D[3]
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
set_location_assignment PIN_J10 -to EX_IO[0]
set_location_assignment PIN_J14 -to EX_IO[1]
set_location_assignment PIN_H13 -to EX_IO[2]
set_location_assignment PIN_H14 -to EX_IO[3]
set_location_assignment PIN_F14 -to EX_IO[4]
set_location_assignment PIN_E10 -to EX_IO[5]
set_location_assignment PIN_D9 -to EX_IO[6]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

60
1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.qsf.bak Normal file
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@ -0,0 +1,60 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 12:24:51 November 18, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# MuxDemo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY Mux16_1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:24:51 NOVEMBER 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name BDF_FILE Mux16_1.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Mux16_1.vwf

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1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.cmp.logdb
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@ -1,63 +1 @@
v1 v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;0;0;0;0;21;0;0;0;0;0;0;0;1;0;0;0;20;1;0;20;0;0;1;0;21;21;21;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,21;21;21;21;21;0;21;21;21;21;21;21;21;20;21;21;21;1;20;21;1;21;21;20;21;0;0;0;21;21,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Y,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I10,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Sel2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I9,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Sel1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I8,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I11,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Sel4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Sel3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I13,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I14,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I12,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,I15,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

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1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.cmp.rdb
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1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.db_info
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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016 Version_Index = 520278016
Creation_Time = Wed Jan 25 23:17:08 2023 Creation_Time = Thu Mar 9 17:16:16 2023

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1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.fit.qmsg
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1674690113139 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678382521345 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1674690113139 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678382521345 ""}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "MuxDemo EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design MuxDemo" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1674690113221 ""} { "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "MuxDemo EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design MuxDemo" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1678382521435 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1674690113260 ""} { "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1678382521479 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1674690113260 ""} { "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1678382521479 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1674690113328 ""} { "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678382521552 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1674690113331 ""} { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678382521556 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C6 " "Device EP4CE10E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1674690113358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C6 " "Device EP4CE15E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1674690113358 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C6 " "Device EP4CE22E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1674690113358 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1674690113358 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "LEDG\[8\] PIN_F17 " "Can't place node \"LEDG\[8\]\" -- illegal location assignment PIN_F17" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { LEDG[8] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 96 592 768 112 "LEDG" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 22 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 75 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1674690113360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 77 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1674690113360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 79 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1674690113360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 81 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1674690113360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 83 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1674690113360 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1674690113360 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[10\] PIN_AC24 " "Can't place node \"SW\[10\]\" -- illegal location assignment PIN_AC24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[10] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 32 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1674690113360 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[1\] PIN_M21 " "Can't place node \"KEY\[1\]\" -- illegal location assignment PIN_M21" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 25 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "21 21 " "No exact pin location assignment(s) for 21 pins of 21 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1674690113532 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[9\] PIN_AB25 " "Can't place node \"SW\[9\]\" -- illegal location assignment PIN_AB25" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[9] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "MuxDemo.sdc " "Synopsys Design Constraints File file not found: 'MuxDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1674690113590 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[0\] PIN_M23 " "Can't place node \"KEY\[0\]\" -- illegal location assignment PIN_M23" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 26 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1674690113590 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[8\] PIN_AC25 " "Can't place node \"SW\[8\]\" -- illegal location assignment PIN_AC25" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[8] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 34 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1674690113590 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[11\] PIN_AB24 " "Can't place node \"SW\[11\]\" -- illegal location assignment PIN_AB24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[11] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1674690113591 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[3\] PIN_R24 " "Can't place node \"KEY\[3\]\" -- illegal location assignment PIN_R24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 23 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1674690113591 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[5\] PIN_AC26 " "Can't place node \"SW\[5\]\" -- illegal location assignment PIN_AC26" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 37 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1674690113591 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[6\] PIN_AD26 " "Can't place node \"SW\[6\]\" -- illegal location assignment PIN_AD26" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 36 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1674690113591 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[4\] PIN_AB27 " "Can't place node \"SW\[4\]\" -- illegal location assignment PIN_AB27" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 38 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[7\] PIN_AB26 " "Can't place node \"SW\[7\]\" -- illegal location assignment PIN_AB26" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[2\] PIN_N21 " "Can't place node \"KEY\[2\]\" -- illegal location assignment PIN_N21" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 24 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[2\] PIN_AC27 " "Can't place node \"SW\[2\]\" -- illegal location assignment PIN_AC27" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[1\] PIN_AC28 " "Can't place node \"SW\[1\]\" -- illegal location assignment PIN_AC28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[0\] PIN_AB28 " "Can't place node \"SW\[0\]\" -- illegal location assignment PIN_AB28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[3\] PIN_AD27 " "Can't place node \"SW\[3\]\" -- illegal location assignment PIN_AD27" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[13\] PIN_AA24 " "Can't place node \"SW\[13\]\" -- illegal location assignment PIN_AA24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[13] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[14\] PIN_AA23 " "Can't place node \"SW\[14\]\" -- illegal location assignment PIN_AA23" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[14] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 28 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1674690113593 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[12\] PIN_AB23 " "Can't place node \"SW\[12\]\" -- illegal location assignment PIN_AB23" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[12] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 30 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1674690113594 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1674690113594 ""} { "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[15\] PIN_AA22 " "Can't place node \"SW\[15\]\" -- illegal location assignment PIN_AA22" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[15] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "21 unused 2.5V 20 1 0 " "Number of I/O pins in group: 21 (unused VREF, 2.5V VCCIO, 20 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1674690113594 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1674690113594 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1674690113594 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 7 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 8 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 13 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 9 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 13 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 12 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1674690113595 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1674690113595 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1674690113595 ""} { "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678382521597 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1674690113601 ""} { "Error" "EFITCC_FITCC_FAIL" "" "Can't fit design in device" { } { } 0 171000 "Can't fit design in device" 0 0 "Fitter" 0 -1 1678382521597 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1674690113602 ""} { "Error" "EQEXE_ERROR_COUNT" "Fitter 22 s 3 s Quartus Prime " "Quartus Prime Fitter was unsuccessful. 22 errors, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "386 " "Peak virtual memory: 386 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678382521619 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Mar 9 17:22:01 2023 " "Processing ended: Thu Mar 9 17:22:01 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678382521619 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678382521619 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678382521619 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678382521619 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1674690113856 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1674690113868 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1674690113875 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1674690113922 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1674690113922 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1674690114033 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y0 X34_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y11" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y0 to location X34_Y11"} { { 12 { 0 ""} 23 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1674690114264 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1674690114264 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1674690114282 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1674690114282 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1674690114282 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1674690114283 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1674690114355 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1674690114358 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1674690114448 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1674690114448 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1674690114645 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1674690114877 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/output_files/MuxDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/output_files/MuxDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1674690115045 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "941 " "Peak virtual memory: 941 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1674690115148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 25 23:41:55 2023 " "Processing ended: Wed Jan 25 23:41:55 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1674690115148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1674690115148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1674690115148 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1674690115148 ""}

56
1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.hier_info
View File

@ -1,4 +1,28 @@
|Mux16_1 |MuxDemo
LEDG[8] <= Mux16_1:inst.Y
KEY[0] => Mux16_1:inst.Sel1
KEY[1] => Mux16_1:inst.Sel2
KEY[2] => Mux16_1:inst.Sel3
KEY[3] => Mux16_1:inst.Sel4
SW[0] => Mux16_1:inst.I0
SW[1] => Mux16_1:inst.I1
SW[2] => Mux16_1:inst.I2
SW[3] => Mux16_1:inst.I3
SW[4] => Mux16_1:inst.I4
SW[5] => Mux16_1:inst.I5
SW[6] => Mux16_1:inst.I6
SW[7] => Mux16_1:inst.I7
SW[8] => Mux16_1:inst.I8
SW[9] => Mux16_1:inst.I9
SW[10] => Mux16_1:inst.I10
SW[11] => Mux16_1:inst.I11
SW[12] => Mux16_1:inst.I12
SW[13] => Mux16_1:inst.I13
SW[14] => Mux16_1:inst.I14
SW[15] => Mux16_1:inst.I15
|MuxDemo|Mux16_1:inst
Y <= Mux2_1:inst14.Y Y <= Mux2_1:inst14.Y
Sel4 => Mux2_1:inst14.S Sel4 => Mux2_1:inst14.S
Sel3 => Mux2_1:inst12.S Sel3 => Mux2_1:inst12.S
@ -33,7 +57,7 @@ I14 => Mux2_1:inst9.I0
I15 => Mux2_1:inst9.I1 I15 => Mux2_1:inst9.I1
|Mux16_1|Mux2_1:inst14 |MuxDemo|Mux16_1:inst|Mux2_1:inst14
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -41,7 +65,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst12 |MuxDemo|Mux16_1:inst|Mux2_1:inst12
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -49,7 +73,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst4 |MuxDemo|Mux16_1:inst|Mux2_1:inst4
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -57,7 +81,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst |MuxDemo|Mux16_1:inst|Mux2_1:inst
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -65,7 +89,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst1 |MuxDemo|Mux16_1:inst|Mux2_1:inst1
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -73,7 +97,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst5 |MuxDemo|Mux16_1:inst|Mux2_1:inst5
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -81,7 +105,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst2 |MuxDemo|Mux16_1:inst|Mux2_1:inst2
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -89,7 +113,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst3 |MuxDemo|Mux16_1:inst|Mux2_1:inst3
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -97,7 +121,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst13 |MuxDemo|Mux16_1:inst|Mux2_1:inst13
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -105,7 +129,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst10 |MuxDemo|Mux16_1:inst|Mux2_1:inst10
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -113,7 +137,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst6 |MuxDemo|Mux16_1:inst|Mux2_1:inst6
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -121,7 +145,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst7 |MuxDemo|Mux16_1:inst|Mux2_1:inst7
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -129,7 +153,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst11 |MuxDemo|Mux16_1:inst|Mux2_1:inst11
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -137,7 +161,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst8 |MuxDemo|Mux16_1:inst|Mux2_1:inst8
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1
@ -145,7 +169,7 @@ S => inst3.IN0
I0 => inst.IN0 I0 => inst.IN0
|Mux16_1|Mux2_1:inst9 |MuxDemo|Mux16_1:inst|Mux2_1:inst9
Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE Y <= inst2.DB_MAX_OUTPUT_PORT_TYPE
I1 => inst1.IN0 I1 => inst1.IN0
S => inst1.IN1 S => inst1.IN1

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1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.lpc.html
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@ -16,7 +16,7 @@
<TH>Output only Bidir</TH> <TH>Output only Bidir</TH>
</TR> </TR>
<TR > <TR >
<TD >inst9</TD> <TD >inst|inst9</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -32,7 +32,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst8</TD> <TD >inst|inst8</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -48,7 +48,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst11</TD> <TD >inst|inst11</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -64,7 +64,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst7</TD> <TD >inst|inst7</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -80,7 +80,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst6</TD> <TD >inst|inst6</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -96,7 +96,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst10</TD> <TD >inst|inst10</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -112,7 +112,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst13</TD> <TD >inst|inst13</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -128,7 +128,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst3</TD> <TD >inst|inst3</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -144,7 +144,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst2</TD> <TD >inst|inst2</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -160,7 +160,7 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst5</TD> <TD >inst|inst5</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -176,7 +176,71 @@
<TD >0</TD> <TD >0</TD>
</TR> </TR>
<TR > <TR >
<TD >inst1</TD> <TD >inst|inst1</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|inst</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|inst4</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|inst12</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst|inst14</TD>
<TD >3</TD> <TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@ -193,55 +257,7 @@
</TR> </TR>
<TR > <TR >
<TD >inst</TD> <TD >inst</TD>
<TD >3</TD> <TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst4</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst12</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst14</TD>
<TD >3</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>

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1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.lpc.txt
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@ -1,21 +1,22 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ; ; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst9 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst9 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst8 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst8 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst11 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst11 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst7 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst7 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst6 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst6 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst10 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst10 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst13 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst13 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst3 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst3 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst2 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst2 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst5 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst5 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst1 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst1 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst4 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst4 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst12 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst12 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst14 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst|inst14 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; inst ; 20 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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@ -1,13 +1,15 @@
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1674690106501 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 25 23:41:46 2023 " "Processing started: Wed Jan 25 23:41:46 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1674690106501 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1674690106501 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678382513352 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 17:21:53 2023 " "Processing started: Thu Mar 9 17:21:53 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678382513352 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382513352 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1674690106501 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382513352 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1674690106594 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678382513490 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1674690106594 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678382513490 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux16_1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Mux16_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Mux16_1 " "Found entity 1: Mux16_1" { } { { "Mux16_1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/Mux16_1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1674690111390 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1674690111390 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux16_1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Mux16_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Mux16_1 " "Found entity 1: Mux16_1" { } { { "Mux16_1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux16_1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678382519004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382519004 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Mux16_1 " "Elaborating entity \"Mux16_1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1674690111423 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MuxDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file MuxDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 MuxDemo " "Found entity 1: MuxDemo" { } { { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678382519005 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382519005 ""}
{ "Warning" "WSGN_SEARCH_FILE" "Mux2_1.bdf 1 1 " "Using design file Mux2_1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1 " "Found entity 1: Mux2_1" { } { { "Mux2_1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/Mux2_1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1674690111428 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1674690111428 ""} { "Info" "ISGN_START_ELABORATION_TOP" "MuxDemo " "Elaborating entity \"MuxDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678382519037 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux2_1 Mux2_1:inst14 " "Elaborating entity \"Mux2_1\" for hierarchy \"Mux2_1:inst14\"" { } { { "Mux16_1.bdf" "inst14" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/Mux16_1.bdf" { { 328 688 784 424 "inst14" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1674690111429 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux16_1 Mux16_1:inst " "Elaborating entity \"Mux16_1\" for hierarchy \"Mux16_1:inst\"" { } { { "MuxDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 72 488 584 456 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678382519040 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1674690112339 ""} { "Warning" "WSGN_SEARCH_FILE" "Mux2_1.bdf 1 1 " "Using design file Mux2_1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1 " "Found entity 1: Mux2_1" { } { { "Mux2_1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux2_1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678382519043 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1678382519043 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1674690112561 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1674690112561 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux2_1 Mux16_1:inst\|Mux2_1:inst14 " "Elaborating entity \"Mux2_1\" for hierarchy \"Mux16_1:inst\|Mux2_1:inst14\"" { } { { "Mux16_1.bdf" "inst14" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux16_1.bdf" { { 328 688 784 424 "inst14" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678382519043 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "31 " "Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1674690112576 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1674690112576 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1674690112576 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1674690112576 ""} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678382519976 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "402 " "Peak virtual memory: 402 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1674690112580 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 25 23:41:52 2023 " "Processing ended: Wed Jan 25 23:41:52 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1674690112580 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1674690112580 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1674690112580 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1674690112580 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678382520229 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678382520229 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "31 " "Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678382520254 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678382520254 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678382520254 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678382520254 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678382520258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 17:22:00 2023 " "Processing ended: Thu Mar 9 17:22:00 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678382520258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678382520258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678382520258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382520258 ""}

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@ -1 +1 @@
SOURCE FIT

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@ -1,7 +1,2 @@
start_full_compilation:s:00:00:12 start_analysis_synthesis:s:00:00:08-start_full_compilation
start_analysis_synthesis:s:00:00:07-start_full_compilation
start_analysis_elaboration:s-start_full_compilation start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:03-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation
start_eda_netlist_writer:s:00:00:00-start_full_compilation

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@ -4,87 +4,87 @@
"name" : "Top", "name" : "Top",
"pins" : [ "pins" : [
{ {
"name" : "Y", "name" : "LEDG[8]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I10", "name" : "SW[10]",
"strict" : false "strict" : false
}, },
{ {
"name" : "Sel2", "name" : "KEY[1]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I9", "name" : "SW[9]",
"strict" : false "strict" : false
}, },
{ {
"name" : "Sel1", "name" : "KEY[0]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I8", "name" : "SW[8]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I11", "name" : "SW[11]",
"strict" : false "strict" : false
}, },
{ {
"name" : "Sel4", "name" : "KEY[3]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I5", "name" : "SW[5]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I6", "name" : "SW[6]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I4", "name" : "SW[4]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I7", "name" : "SW[7]",
"strict" : false "strict" : false
}, },
{ {
"name" : "Sel3", "name" : "KEY[2]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I2", "name" : "SW[2]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I1", "name" : "SW[1]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I0", "name" : "SW[0]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I3", "name" : "SW[3]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I13", "name" : "SW[13]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I14", "name" : "SW[14]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I12", "name" : "SW[12]",
"strict" : false "strict" : false
}, },
{ {
"name" : "I15", "name" : "SW[15]",
"strict" : false "strict" : false
} }
] ]

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1580
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4
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@ -1,7 +1,7 @@
Fitter Status : Successful - Wed Jan 25 23:41:55 2023 Fitter Status : Failed - Thu Mar 9 17:22:01 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : MuxDemo Revision Name : MuxDemo
Top-level Entity Name : Mux16_1 Top-level Entity Name : MuxDemo
Family : Cyclone IV E Family : Cyclone IV E
Device : EP4CE6E22C6 Device : EP4CE6E22C6
Timing Models : Final Timing Models : Final

45
1ano/1semestre/isd/quartus-projects/MuxDemo/output_files/MuxDemo.flow.rpt
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@ -1,5 +1,5 @@
Flow report for MuxDemo Flow report for MuxDemo
Wed Jan 25 23:43:19 2023 Thu Mar 9 17:22:01 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -41,10 +41,10 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Wed Jan 25 23:43:19 2023 ; ; Flow Status ; Flow Failed - Thu Mar 9 17:22:01 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; MuxDemo ; ; Revision Name ; MuxDemo ;
; Top-level Entity Name ; Mux16_1 ; ; Top-level Entity Name ; MuxDemo ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Total logic elements ; 10 / 6,272 ( < 1 % ) ; ; Total logic elements ; 10 / 6,272 ( < 1 % ) ;
; Total combinational functions ; 10 / 6,272 ( < 1 % ) ; ; Total combinational functions ; 10 / 6,272 ( < 1 % ) ;
@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 01/25/2023 23:41:46 ; ; Start date & time ; 03/09/2023 17:21:53 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; MuxDemo ; ; Revision Name ; MuxDemo ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 59579634461495.167469010663258 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 198516037997543.167838251310188 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@ -84,11 +84,10 @@ https://fpgasoftware.intel.com/eula.
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ; ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Mux16_1 ; Top ; ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Mux16_1 ; Top ; ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Mux16_1 ; Top ; ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; Mux16_1 ; MuxDemo ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
@ -97,15 +96,9 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 396 MB ; 00:00:14 ; ; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 397 MB ; 00:00:17 ;
; Fitter ; 00:00:03 ; 1.0 ; 941 MB ; 00:00:02 ; ; Fitter ; 00:00:00 ; 1.0 ; 386 MB ; 00:00:00 ;
; Assembler ; 00:00:00 ; 1.0 ; 353 MB ; 00:00:00 ; ; Total ; 00:00:07 ; -- ; -- ; 00:00:17 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 465 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 600 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 595 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 595 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 603 MB ; 00:00:00 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:17 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
@ -114,14 +107,8 @@ https://fpgasoftware.intel.com/eula.
+----------------------+------------------+----------------+------------+----------------+ +----------------------+------------------+----------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+----------------+------------+----------------+ +----------------------+------------------+----------------+------------+----------------+
; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ; ; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Fitter ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ; ; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Assembler ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
+----------------------+------------------+----------------+------------+----------------+ +----------------------+------------------+----------------+------------+----------------+
@ -130,12 +117,6 @@ https://fpgasoftware.intel.com/eula.
------------ ------------
quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo
quartus_fit --read_settings_files=off --write_settings_files=off MuxDemo -c MuxDemo quartus_fit --read_settings_files=off --write_settings_files=off MuxDemo -c MuxDemo
quartus_asm --read_settings_files=off --write_settings_files=off MuxDemo -c MuxDemo
quartus_sta MuxDemo -c MuxDemo
quartus_eda --read_settings_files=off --write_settings_files=off MuxDemo -c MuxDemo
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off MuxDemo -c MuxDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/Waveform1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/simulation/qsim/Waveform1.vwf.vht
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off MuxDemo -c MuxDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/Mux16_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/simulation/qsim/Waveform1.vwf.vht
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/simulation/qsim/ MuxDemo -c MuxDemo

119
1ano/1semestre/isd/quartus-projects/MuxDemo/output_files/MuxDemo.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for MuxDemo Analysis & Synthesis report for MuxDemo
Wed Jan 25 23:41:52 2023 Thu Mar 9 17:22:00 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -43,10 +43,10 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jan 25 23:41:52 2023 ; ; Analysis & Synthesis Status ; Successful - Thu Mar 9 17:22:00 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; MuxDemo ; ; Revision Name ; MuxDemo ;
; Top-level Entity Name ; Mux16_1 ; ; Top-level Entity Name ; MuxDemo ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Total logic elements ; 10 ; ; Total logic elements ; 10 ;
; Total combinational functions ; 10 ; ; Total combinational functions ; 10 ;
@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ; ; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name ; Mux16_1 ; MuxDemo ; ; Top-level entity name ; MuxDemo ; MuxDemo ;
; Family name ; Cyclone IV E ; Cyclone V ; ; Family name ; Cyclone IV E ; Cyclone V ;
; Use smart compilation ; Off ; Off ; ; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
@ -161,56 +161,58 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+ +----------------------------+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ; ; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------------------------------------+---------+ +----------------------------------+-----------------+------------------------------------------+------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------------------------------------+---------+ +----------------------------------+-----------------+------------------------------------------+------------------------------------------------------------------------------------------+---------+
; Mux16_1.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/Mux16_1.bdf ; ; ; Mux16_1.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux16_1.bdf ; ;
; Mux2_1.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/MuxDemo/Mux2_1.bdf ; ; ; MuxDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf ; ;
+----------------------------------+-----------------+------------------------------------------+--------------------------------------------------------------------------------+---------+ ; Mux2_1.bdf ; yes ; Auto-Found Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux2_1.bdf ; ;
+----------------------------------+-----------------+------------------------------------------+------------------------------------------------------------------------------------------+---------+
+----------------------------------------------------------+ +------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ; ; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------+ +---------------------------------------------+--------------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+------------+ +---------------------------------------------+--------------+
; Estimated Total logic elements ; 10 ; ; Estimated Total logic elements ; 10 ;
; ; ; ; ; ;
; Total combinational functions ; 10 ; ; Total combinational functions ; 10 ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 10 ; ; -- 4 input functions ; 10 ;
; -- 3 input functions ; 0 ; ; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ; ; -- <=2 input functions ; 0 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 10 ; ; -- normal mode ; 10 ;
; -- arithmetic mode ; 0 ; ; -- arithmetic mode ; 0 ;
; ; ; ; ; ;
; Total registers ; 0 ; ; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ; ; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ; ; -- I/O registers ; 0 ;
; ; ; ; ; ;
; I/O pins ; 21 ; ; I/O pins ; 21 ;
; ; ; ; ; ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ;
; ; ; ; ; ;
; Maximum fan-out node ; Sel2~input ; ; Maximum fan-out node ; KEY[1]~input ;
; Maximum fan-out ; 6 ; ; Maximum fan-out ; 6 ;
; Total fan-out ; 62 ; ; Total fan-out ; 62 ;
; Average fan-out ; 1.19 ; ; Average fan-out ; 1.19 ;
+---------------------------------------------+------------+ +---------------------------------------------+--------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ; ; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+ +----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+ +----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+-------------+--------------+
; |Mux16_1 ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; |Mux16_1 ; Mux16_1 ; work ; ; |MuxDemo ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; |MuxDemo ; MuxDemo ; work ;
; |Mux2_1:inst14| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Mux16_1|Mux2_1:inst14 ; Mux2_1 ; work ; ; |Mux16_1:inst| ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MuxDemo|Mux16_1:inst ; Mux16_1 ; work ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+ ; |Mux2_1:inst14| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |MuxDemo|Mux16_1:inst|Mux2_1:inst14 ; Mux2_1 ; work ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -259,16 +261,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Jan 25 23:41:46 2023 Info: Processing started: Thu Mar 9 17:21:53 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file Mux16_1.bdf Info (12021): Found 1 design units, including 1 entities, in source file Mux16_1.bdf
Info (12023): Found entity 1: Mux16_1 Info (12023): Found entity 1: Mux16_1
Info (12127): Elaborating entity "Mux16_1" for the top level hierarchy Info (12021): Found 1 design units, including 1 entities, in source file MuxDemo.bdf
Info (12023): Found entity 1: MuxDemo
Info (12127): Elaborating entity "MuxDemo" for the top level hierarchy
Info (12128): Elaborating entity "Mux16_1" for hierarchy "Mux16_1:inst"
Warning (12125): Using design file Mux2_1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Warning (12125): Using design file Mux2_1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: Mux2_1 Info (12023): Found entity 1: Mux2_1
Info (12128): Elaborating entity "Mux2_1" for hierarchy "Mux2_1:inst14" Info (12128): Elaborating entity "Mux2_1" for hierarchy "Mux16_1:inst|Mux2_1:inst14"
Info (286030): Timing-Driven Synthesis is running Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
@ -277,9 +282,9 @@ Info (21057): Implemented 31 device resources after synthesis - the final resour
Info (21059): Implemented 1 output pins Info (21059): Implemented 1 output pins
Info (21061): Implemented 10 logic cells Info (21061): Implemented 10 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 402 megabytes Info: Peak virtual memory: 400 megabytes
Info: Processing ended: Wed Jan 25 23:41:52 2023 Info: Processing ended: Thu Mar 9 17:22:00 2023
Info: Elapsed time: 00:00:06 Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:14 Info: Total CPU time (on all processors): 00:00:17

4
1ano/1semestre/isd/quartus-projects/MuxDemo/output_files/MuxDemo.map.summary
View File

@ -1,7 +1,7 @@
Analysis & Synthesis Status : Successful - Wed Jan 25 23:41:52 2023 Analysis & Synthesis Status : Successful - Thu Mar 9 17:22:00 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : MuxDemo Revision Name : MuxDemo
Top-level Entity Name : Mux16_1 Top-level Entity Name : MuxDemo
Family : Cyclone IV E Family : Cyclone IV E
Total logic elements : 10 Total logic elements : 10
Total combinational functions : 10 Total combinational functions : 10

216
1ano/1semestre/isd/quartus-projects/MuxDemo/output_files/MuxDemo.pin
View File

@ -1,216 +0,0 @@
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 2.5V
-- Bank 2: 2.5V
-- Bank 3: 2.5V
-- Bank 4: 2.5V
-- Bank 5: 2.5V
-- Bank 6: 2.5V
-- Bank 7: 2.5V
-- Bank 8: 2.5V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
CHIP "MuxDemo" ASSIGNED TO AN: EP4CE6E22C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 3 : : : : 1 :
GND : 4 : gnd : : : :
VCCINT : 5 : power : : 1.2V : :
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : input : 2.5 V : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : 7 : : : : 1 :
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : input : 2.5 V : : 1 : N
nSTATUS : 9 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 :
~ALTERA_DCLK~ : 12 : output : 2.5 V : : 1 : N
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : input : 2.5 V : : 1 : N
nCONFIG : 14 : : : : 1 :
TDI : 15 : input : : : 1 :
TCK : 16 : input : : : 1 :
VCCIO1 : 17 : power : : 2.5V : 1 :
TMS : 18 : input : : : 1 :
GND : 19 : gnd : : : :
TDO : 20 : output : : : 1 :
nCE : 21 : : : : 1 :
GND : 22 : gnd : : : :
GND+ : 23 : : : : 1 :
GND+ : 24 : : : : 2 :
GND+ : 25 : : : : 2 :
VCCIO2 : 26 : power : : 2.5V : 2 :
GND : 27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 28 : : : : 2 :
VCCINT : 29 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 30 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 31 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 32 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 33 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 34 : : : : 2 :
VCCA1 : 35 : power : : 2.5V : :
GNDA1 : 36 : gnd : : : :
VCCD_PLL1 : 37 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 :
VCCIO3 : 40 : power : : 2.5V : 3 :
GND : 41 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 :
VCCINT : 45 : power : : 1.2V : :
I10 : 46 : input : 2.5 V : : 3 : N
VCCIO3 : 47 : power : : 2.5V : 3 :
GND : 48 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 53 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 54 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 4 :
VCCIO4 : 56 : power : : 2.5V : 4 :
GND : 57 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 :
VCCINT : 61 : power : : 1.2V : :
VCCIO4 : 62 : power : : 2.5V : 4 :
GND : 63 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 :
I9 : 65 : input : 2.5 V : : 4 : N
I13 : 66 : input : 2.5 V : : 4 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 :
I8 : 68 : input : 2.5 V : : 4 : N
I4 : 69 : input : 2.5 V : : 4 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 5 :
I2 : 74 : input : 2.5 V : : 5 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : 75 : : : : 5 :
Y : 76 : output : 2.5 V : : 5 : N
I15 : 77 : input : 2.5 V : : 5 : N
VCCINT : 78 : power : : 1.2V : :
GND : 79 : gnd : : : :
Sel2 : 80 : input : 2.5 V : : 5 : N
VCCIO5 : 81 : power : : 2.5V : 5 :
GND : 82 : gnd : : : :
I12 : 83 : input : 2.5 V : : 5 : N
I3 : 84 : input : 2.5 V : : 5 : N
I5 : 85 : input : 2.5 V : : 5 : N
I6 : 86 : input : 2.5 V : : 5 : N
I11 : 87 : input : 2.5 V : : 5 : N
I7 : 88 : input : 2.5 V : : 5 : N
Sel3 : 89 : input : 2.5 V : : 5 : N
I1 : 90 : input : 2.5 V : : 6 : N
I0 : 91 : input : 2.5 V : : 6 : N
CONF_DONE : 92 : : : : 6 :
VCCIO6 : 93 : power : : 2.5V : 6 :
MSEL0 : 94 : : : : 6 :
GND : 95 : gnd : : : :
MSEL1 : 96 : : : : 6 :
MSEL2 : 97 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 :
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 101 : output : 2.5 V : : 6 : N
VCCINT : 102 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 105 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 6 :
VCCA2 : 107 : power : : 2.5V : :
GNDA2 : 108 : gnd : : : :
VCCD_PLL2 : 109 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 7 :
Sel1 : 112 : input : 2.5 V : : 7 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 115 : : : : 7 :
VCCINT : 116 : power : : 1.2V : :
VCCIO7 : 117 : power : : 2.5V : 7 :
GND : 118 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 119 : : : : 7 :
I14 : 120 : input : 2.5 V : : 7 : N
Sel4 : 121 : input : 2.5 V : : 7 : N
VCCIO7 : 122 : power : : 2.5V : 7 :
GND : 123 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 124 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 125 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 126 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 127 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 128 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 129 : : : : 8 :
VCCIO8 : 130 : power : : 2.5V : 8 :
GND : 131 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 132 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 133 : : : : 8 :
VCCINT : 134 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 135 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 136 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 137 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 138 : : : : 8 :
VCCIO8 : 139 : power : : 2.5V : 8 :
GND : 140 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 141 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 8 :
GND : EPAD : : : : :