22 lines
424 B
VHDL
22 lines
424 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity FlipFlopD_Demo is
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port(
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SW : in std_logic_vector(2 downto 0);
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KEY : in std_logic_vector(1 downto 0);
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LEDR : out std_logic_vector(1 downto 0)
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);
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end FlipFlopD_Demo;
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architecture Shell of FlipFlopD_Demo is
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begin
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ff_d : entity work.FlipFlopD(BehavS)
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port map(
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clk => not KEY(0),
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d => SW(0),
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set => SW(1),
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rst => SW(2),
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q => LEDR(0)
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);
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end Shell;
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