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TiagoRG 2630762c1f
[LSD] pratica04 CounterDemo enable/disable added and added FreqDevider 
by itself
 		2023-04-04 22:06:30 +01:00
..
CounterDemo [LSD] pratica04 CounterDemo enable/disable added and added FreqDevider 2023-04-04 22:06:30 +01:00
FlipFlopD_Demo [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
FreqDivider_Demo [LSD] pratica04 CounterDemo enable/disable added and added FreqDevider 2023-04-04 22:06:30 +01:00
RegisterDemo [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
LSD_2022-23_TrabPrat04.pdf [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
README.md [LSD] README update 2023-04-04 18:20:08 +01:00

README.md

Laboratórios de Sistemas Digitais

Trabalho prático 04

Tópico principal da aula: Modelação em VHDL, simulação e implementação de circuitos sequenciais elementares

Pode conter erros, caso encontre algum, crie um ticket