uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/VHDLDemo.msim.vcd

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$comment
File created using the following command:
vcd file VHDLDemo.msim.vcd -direction
$end
$date
Sat Feb 18 15:33:50 2023
$end
$version
ModelSim Version 2020.1
$end
$timescale
1ps
$end
$scope module and2gate_vhd_vec_tst $end
$var wire 1 ! inPort0 $end
$var wire 1 " inPort1 $end
$var wire 1 # outPort $end
$scope module i1 $end
$var wire 1 $ gnd $end
$var wire 1 % vcc $end
$var wire 1 & unknown $end
$var wire 1 ' devoe $end
$var wire 1 ( devclrn $end
$var wire 1 ) devpor $end
$var wire 1 * ww_devoe $end
$var wire 1 + ww_devclrn $end
$var wire 1 , ww_devpor $end
$var wire 1 - ww_inPort0 $end
$var wire 1 . ww_inPort1 $end
$var wire 1 / ww_outPort $end
$var wire 1 0 \outPort~output_o\ $end
$var wire 1 1 \inPort0~input_o\ $end
$var wire 1 2 \inPort1~input_o\ $end
$var wire 1 3 \outPort~0_combout\ $end
$upscope $end
$upscope $end
$enddefinitions $end
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$end
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