TiagoRG 4d23ebbdc1 LSD aula01 initial commit, base VHDL files, to be finished along the hardware		2023-02-20 22:37:38 +00:00
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db	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
incremental_db	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
output_files	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
simulation	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.qsf	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.qsf.bak	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.qws	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.vhd	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.vhd.bak	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.vwf	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
GateDemo.vhd	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
GateDemo.vhd.bak	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
NAND2Gate.vhd	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
NAND2Gate.vhd.bak	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
NOTGate.vhd	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
VHDLDemo.qpf	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00