16 lines
7.7 KiB
Plaintext
16 lines
7.7 KiB
Plaintext
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676735141944 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676735141945 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 15:45:41 2023 " "Processing started: Sat Feb 18 15:45:41 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676735141945 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676735141945 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676735141945 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676735142083 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676735142083 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND2Gate-Behavioral " "Found design unit 1: AND2Gate-Behavioral" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676735147422 ""} { "Info" "ISGN_ENTITY_NAME" "1 AND2Gate " "Found entity 1: AND2Gate" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676735147422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676735147422 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file GateDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GateDemo-Shell " "Found design unit 1: GateDemo-Shell" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676735147422 ""} { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676735147422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676735147422 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676735147452 ""}
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{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] GateDemo.vhd(7) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at GateDemo.vhd(7)" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 7 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1676735147452 "|GateDemo"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AND2Gate AND2Gate:system_core A:behavioral " "Elaborating entity \"AND2Gate\" using architecture \"A:behavioral\" for hierarchy \"AND2Gate:system_core\"" { } { { "GateDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 13 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676735147456 ""}
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{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1676735147792 "|GateDemo|LEDR[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1676735147792 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676735147856 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676735148219 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676735148219 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676735148235 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676735148235 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676735148235 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676735148235 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676735148238 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:45:48 2023 " "Processing ended: Sat Feb 18 15:45:48 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676735148238 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676735148238 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676735148238 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676735148238 ""}
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