19 lines
390 B
VHDL
19 lines
390 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity GateDemo is
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port (
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SW : in std_logic_vector(1 downto 0);
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LEDR : out std_logic_vector(1 downto 0)
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);
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end GateDemo;
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architecture Shell of GateDemo is
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begin
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system_core: entity work.AND2Gate(Behavioral)
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port map(
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inPort0 => SW(0),
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inPort1 => SW(1),
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outPort => LEDR(0)
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);
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end Shell;
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