202 lines
15 KiB
Plaintext
202 lines
15 KiB
Plaintext
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Analysis & Synthesis report for AdderDemo
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Thu Dec 1 16:53:38 2022
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+---------------------------------------------+
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; Analysis & Synthesis Status ; Failed - Thu Dec 1 16:53:38 2022 ;
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; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
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; Revision Name ; AdderDemo ;
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; Top-level Entity Name ; Adder ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; N/A until Partition Merge ;
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; Total combinational functions ; N/A until Partition Merge ;
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; Dedicated logic registers ; N/A until Partition Merge ;
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; Total registers ; N/A until Partition Merge ;
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; Total pins ; N/A until Partition Merge ;
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; Total virtual pins ; N/A until Partition Merge ;
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; Total memory bits ; N/A until Partition Merge ;
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; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
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; Total PLLs ; N/A until Partition Merge ;
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+------------------------------------+---------------------------------------------+
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+------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Top-level entity name ; Adder ; AdderDemo ;
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; Family name ; Cyclone IV E ; Cyclone V ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto RAM Block Balancing ; On ; On ;
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; Auto RAM to Logic Cell Conversion ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 2 ; 2 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Resource Aware Inference For Block RAM ; On ; On ;
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+------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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+----------------------------+-------------+
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Analysis & Synthesis
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Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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Info: Processing started: Thu Dec 1 16:53:33 2022
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
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Info (12021): Found 1 design units, including 1 entities, in source file AdderDemo.bdf
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Info (12023): Found entity 1: AdderDemo
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Info (12021): Found 1 design units, including 1 entities, in source file Adder.bdf
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Info (12023): Found entity 1: Adder
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Info (12127): Elaborating entity "Adder" for the top level hierarchy
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Info (12128): Elaborating entity "AdderDemo" for hierarchy "AdderDemo:inst6"
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Error (12014): Net "S", which fans out to "S", cannot be assigned more than one value
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Error (12015): Net is fed by "AdderDemo:inst|S"
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Error (12015): Net is fed by "AdderDemo:inst3|S"
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Error (12015): Net is fed by "AdderDemo:inst4|S"
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Error (12015): Net is fed by "AdderDemo:inst6|S"
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Error (12014): Net "AdderDemo:inst|gdfx_temp0", which fans out to "AdderDemo:inst|inst6", cannot be assigned more than one value
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Error (12015): Net is fed by "AdderDemo:inst|Cin"
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Error (12015): Net is fed by "AdderDemo:inst|A"
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Error (12015): Net is fed by "AdderDemo:inst|B"
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Error (12014): Net "AdderDemo:inst3|gdfx_temp0", which fans out to "AdderDemo:inst3|inst6", cannot be assigned more than one value
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Error (12015): Net is fed by "AdderDemo:inst3|Cin"
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Error (12015): Net is fed by "AdderDemo:inst3|A"
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Error (12015): Net is fed by "AdderDemo:inst3|B"
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Error (12014): Net "AdderDemo:inst4|gdfx_temp0", which fans out to "AdderDemo:inst4|inst6", cannot be assigned more than one value
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Error (12015): Net is fed by "AdderDemo:inst4|Cin"
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Error (12015): Net is fed by "AdderDemo:inst4|A"
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Error (12015): Net is fed by "AdderDemo:inst4|B"
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Error (12014): Net "AdderDemo:inst6|gdfx_temp0", which fans out to "AdderDemo:inst6|inst6", cannot be assigned more than one value
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Error (12015): Net is fed by "AdderDemo:inst6|Cin"
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Error (12015): Net is fed by "AdderDemo:inst6|A"
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Error (12015): Net is fed by "AdderDemo:inst6|B"
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Error: Quartus Prime Analysis & Synthesis was unsuccessful. 21 errors, 1 warning
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Error: Peak virtual memory: 352 megabytes
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Error: Processing ended: Thu Dec 1 16:53:38 2022
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Error: Elapsed time: 00:00:05
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Error: Total CPU time (on all processors): 00:00:14
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