Analysis & Synthesis report for AdderDemo Thu Dec 1 16:53:38 2022 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2020 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details, at https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------+ ; Analysis & Synthesis Status ; Failed - Thu Dec 1 16:53:38 2022 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; AdderDemo ; ; Top-level Entity Name ; Adder ; ; Family ; Cyclone IV E ; ; Total logic elements ; N/A until Partition Merge ; ; Total combinational functions ; N/A until Partition Merge ; ; Dedicated logic registers ; N/A until Partition Merge ; ; Total registers ; N/A until Partition Merge ; ; Total pins ; N/A until Partition Merge ; ; Total virtual pins ; N/A until Partition Merge ; ; Total memory bits ; N/A until Partition Merge ; ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ; ; Total PLLs ; N/A until Partition Merge ; +------------------------------------+---------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +------------------------------------------------------------------+--------------------+--------------------+ ; Top-level entity name ; Adder ; AdderDemo ; ; Family name ; Cyclone IV E ; Cyclone V ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; +------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; +----------------------------+-------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Processing started: Thu Dec 1 16:53:33 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (12021): Found 1 design units, including 1 entities, in source file AdderDemo.bdf Info (12023): Found entity 1: AdderDemo Info (12021): Found 1 design units, including 1 entities, in source file Adder.bdf Info (12023): Found entity 1: Adder Info (12127): Elaborating entity "Adder" for the top level hierarchy Info (12128): Elaborating entity "AdderDemo" for hierarchy "AdderDemo:inst6" Error (12014): Net "S", which fans out to "S", cannot be assigned more than one value Error (12015): Net is fed by "AdderDemo:inst|S" Error (12015): Net is fed by "AdderDemo:inst3|S" Error (12015): Net is fed by "AdderDemo:inst4|S" Error (12015): Net is fed by "AdderDemo:inst6|S" Error (12014): Net "AdderDemo:inst|gdfx_temp0", which fans out to "AdderDemo:inst|inst6", cannot be assigned more than one value Error (12015): Net is fed by "AdderDemo:inst|Cin" Error (12015): Net is fed by "AdderDemo:inst|A" Error (12015): Net is fed by "AdderDemo:inst|B" Error (12014): Net "AdderDemo:inst3|gdfx_temp0", which fans out to "AdderDemo:inst3|inst6", cannot be assigned more than one value Error (12015): Net is fed by "AdderDemo:inst3|Cin" Error (12015): Net is fed by "AdderDemo:inst3|A" Error (12015): Net is fed by "AdderDemo:inst3|B" Error (12014): Net "AdderDemo:inst4|gdfx_temp0", which fans out to "AdderDemo:inst4|inst6", cannot be assigned more than one value Error (12015): Net is fed by "AdderDemo:inst4|Cin" Error (12015): Net is fed by "AdderDemo:inst4|A" Error (12015): Net is fed by "AdderDemo:inst4|B" Error (12014): Net "AdderDemo:inst6|gdfx_temp0", which fans out to "AdderDemo:inst6|inst6", cannot be assigned more than one value Error (12015): Net is fed by "AdderDemo:inst6|Cin" Error (12015): Net is fed by "AdderDemo:inst6|A" Error (12015): Net is fed by "AdderDemo:inst6|B" Error: Quartus Prime Analysis & Synthesis was unsuccessful. 21 errors, 1 warning Error: Peak virtual memory: 352 megabytes Error: Processing ended: Thu Dec 1 16:53:38 2022 Error: Elapsed time: 00:00:05 Error: Total CPU time (on all processors): 00:00:14