368 lines
9.5 KiB
Plaintext
368 lines
9.5 KiB
Plaintext
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// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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// DATE "12/02/2022 12:28:32"
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//
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// Device: Altera EP4CE6E22C6 Package TQFP144
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//
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//
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// This Verilog file should be used for ModelSim-Altera (Verilog) only
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//
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`timescale 1 ps/ 1 ps
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module Teste1 (
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Y,
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X1,
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S,
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X0,
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X4,
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X6,
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X2,
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X3,
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X5,
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X7);
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output Y;
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input X1;
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input [2:0] S;
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input X0;
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input X4;
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input X6;
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input X2;
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input X3;
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input X5;
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input X7;
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// Design Ports Information
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// Y => Location: PIN_11, I/O Standard: 2.5 V, Current Strength: Default
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// X3 => Location: PIN_138, I/O Standard: 2.5 V, Current Strength: Default
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// X2 => Location: PIN_137, I/O Standard: 2.5 V, Current Strength: Default
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// S[0] => Location: PIN_141, I/O Standard: 2.5 V, Current Strength: Default
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// S[2] => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default
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// X1 => Location: PIN_10, I/O Standard: 2.5 V, Current Strength: Default
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// X0 => Location: PIN_136, I/O Standard: 2.5 V, Current Strength: Default
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// S[1] => Location: PIN_142, I/O Standard: 2.5 V, Current Strength: Default
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// X7 => Location: PIN_144, I/O Standard: 2.5 V, Current Strength: Default
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// X6 => Location: PIN_2, I/O Standard: 2.5 V, Current Strength: Default
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// X5 => Location: PIN_143, I/O Standard: 2.5 V, Current Strength: Default
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// X4 => Location: PIN_135, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \Y~output_o ;
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wire \X6~input_o ;
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wire \S[2]~input_o ;
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wire \X7~input_o ;
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wire \S[0]~input_o ;
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wire \inst3~3_combout ;
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wire \X5~input_o ;
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wire \X4~input_o ;
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wire \inst3~4_combout ;
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wire \S[1]~input_o ;
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wire \X2~input_o ;
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wire \X3~input_o ;
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wire \inst3~0_combout ;
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wire \X1~input_o ;
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wire \X0~input_o ;
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wire \inst3~1_combout ;
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wire \inst3~2_combout ;
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wire \inst3~5_combout ;
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hard_block auto_generated_inst(
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.devpor(devpor),
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.devclrn(devclrn),
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.devoe(devoe));
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// Location: IOOBUF_X0_Y18_N23
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cycloneive_io_obuf \Y~output (
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.i(\inst3~5_combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\Y~output_o ),
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.obar());
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// synopsys translate_off
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defparam \Y~output .bus_hold = "false";
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defparam \Y~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOIBUF_X0_Y23_N8
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cycloneive_io_ibuf \X6~input (
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.i(X6),
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.ibar(gnd),
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.o(\X6~input_o ));
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// synopsys translate_off
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defparam \X6~input .bus_hold = "false";
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defparam \X6~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X0_Y9_N8
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cycloneive_io_ibuf \S[2]~input (
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.i(S[2]),
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.ibar(gnd),
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.o(\S[2]~input_o ));
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// synopsys translate_off
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defparam \S[2]~input .bus_hold = "false";
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defparam \S[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X1_Y24_N8
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cycloneive_io_ibuf \X7~input (
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.i(X7),
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.ibar(gnd),
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.o(\X7~input_o ));
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// synopsys translate_off
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defparam \X7~input .bus_hold = "false";
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defparam \X7~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X5_Y24_N8
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cycloneive_io_ibuf \S[0]~input (
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.i(S[0]),
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.ibar(gnd),
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.o(\S[0]~input_o ));
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// synopsys translate_off
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defparam \S[0]~input .bus_hold = "false";
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defparam \S[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X5_Y20_N6
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cycloneive_lcell_comb \inst3~3 (
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// Equation(s):
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// \inst3~3_combout = (\S[2]~input_o & ((\S[0]~input_o & ((\X7~input_o ))) # (!\S[0]~input_o & (\X6~input_o ))))
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.dataa(\X6~input_o ),
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.datab(\S[2]~input_o ),
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.datac(\X7~input_o ),
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.datad(\S[0]~input_o ),
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.cin(gnd),
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.combout(\inst3~3_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst3~3 .lut_mask = 16'hC088;
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defparam \inst3~3 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X1_Y24_N1
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cycloneive_io_ibuf \X5~input (
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.i(X5),
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.ibar(gnd),
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.o(\X5~input_o ));
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// synopsys translate_off
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defparam \X5~input .bus_hold = "false";
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defparam \X5~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X11_Y24_N15
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cycloneive_io_ibuf \X4~input (
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.i(X4),
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.ibar(gnd),
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.o(\X4~input_o ));
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// synopsys translate_off
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defparam \X4~input .bus_hold = "false";
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defparam \X4~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X5_Y20_N0
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cycloneive_lcell_comb \inst3~4 (
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// Equation(s):
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// \inst3~4_combout = (\S[2]~input_o & ((\S[0]~input_o & (\X5~input_o )) # (!\S[0]~input_o & ((\X4~input_o )))))
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.dataa(\X5~input_o ),
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.datab(\X4~input_o ),
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.datac(\S[2]~input_o ),
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.datad(\S[0]~input_o ),
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.cin(gnd),
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.combout(\inst3~4_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst3~4 .lut_mask = 16'hA0C0;
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defparam \inst3~4 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X3_Y24_N22
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cycloneive_io_ibuf \S[1]~input (
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.i(S[1]),
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.ibar(gnd),
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.o(\S[1]~input_o ));
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// synopsys translate_off
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defparam \S[1]~input .bus_hold = "false";
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defparam \S[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X7_Y24_N1
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cycloneive_io_ibuf \X2~input (
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.i(X2),
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.ibar(gnd),
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.o(\X2~input_o ));
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// synopsys translate_off
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defparam \X2~input .bus_hold = "false";
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defparam \X2~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X7_Y24_N8
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cycloneive_io_ibuf \X3~input (
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.i(X3),
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.ibar(gnd),
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.o(\X3~input_o ));
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// synopsys translate_off
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defparam \X3~input .bus_hold = "false";
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defparam \X3~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X5_Y20_N24
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cycloneive_lcell_comb \inst3~0 (
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// Equation(s):
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// \inst3~0_combout = (!\S[2]~input_o & ((\S[0]~input_o & ((\X3~input_o ))) # (!\S[0]~input_o & (\X2~input_o ))))
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.dataa(\S[0]~input_o ),
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.datab(\X2~input_o ),
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.datac(\S[2]~input_o ),
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.datad(\X3~input_o ),
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.cin(gnd),
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.combout(\inst3~0_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst3~0 .lut_mask = 16'h0E04;
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defparam \inst3~0 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X0_Y18_N15
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cycloneive_io_ibuf \X1~input (
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.i(X1),
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.ibar(gnd),
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.o(\X1~input_o ));
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// synopsys translate_off
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defparam \X1~input .bus_hold = "false";
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defparam \X1~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X9_Y24_N8
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cycloneive_io_ibuf \X0~input (
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.i(X0),
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.ibar(gnd),
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.o(\X0~input_o ));
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// synopsys translate_off
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defparam \X0~input .bus_hold = "false";
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defparam \X0~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X5_Y20_N10
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cycloneive_lcell_comb \inst3~1 (
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// Equation(s):
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// \inst3~1_combout = (!\S[2]~input_o & ((\S[0]~input_o & (\X1~input_o )) # (!\S[0]~input_o & ((\X0~input_o )))))
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.dataa(\S[0]~input_o ),
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.datab(\X1~input_o ),
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.datac(\S[2]~input_o ),
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.datad(\X0~input_o ),
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.cin(gnd),
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.combout(\inst3~1_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst3~1 .lut_mask = 16'h0D08;
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defparam \inst3~1 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X5_Y20_N28
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cycloneive_lcell_comb \inst3~2 (
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// Equation(s):
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// \inst3~2_combout = (\S[1]~input_o & (\inst3~0_combout )) # (!\S[1]~input_o & ((\inst3~1_combout )))
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.dataa(gnd),
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.datab(\inst3~0_combout ),
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.datac(\S[1]~input_o ),
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.datad(\inst3~1_combout ),
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.cin(gnd),
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.combout(\inst3~2_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst3~2 .lut_mask = 16'hCFC0;
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defparam \inst3~2 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X5_Y20_N26
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cycloneive_lcell_comb \inst3~5 (
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// Equation(s):
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// \inst3~5_combout = (\inst3~2_combout ) # ((\S[1]~input_o & (\inst3~3_combout )) # (!\S[1]~input_o & ((\inst3~4_combout ))))
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.dataa(\inst3~3_combout ),
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.datab(\inst3~4_combout ),
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.datac(\S[1]~input_o ),
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.datad(\inst3~2_combout ),
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.cin(gnd),
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.combout(\inst3~5_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst3~5 .lut_mask = 16'hFFAC;
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defparam \inst3~5 .sum_lutc_input = "datac";
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// synopsys translate_on
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assign Y = \Y~output_o ;
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endmodule
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module hard_block (
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devpor,
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devclrn,
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devoe);
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// Design Ports Information
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// ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default
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// ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA
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input devpor;
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input devclrn;
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input devoe;
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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||
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assign unknown = 1'bx;
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||
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wire \~ALTERA_ASDO_DATA1~~padout ;
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wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
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wire \~ALTERA_DATA0~~padout ;
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||
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wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
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wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
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||
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wire \~ALTERA_DATA0~~ibuf_o ;
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||
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|
||
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|
||
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endmodule
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