// Copyright (C) 2020  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"

// DATE "12/02/2022 12:28:32"

// 
// Device: Altera EP4CE6E22C6 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module Teste1 (
	Y,
	X1,
	S,
	X0,
	X4,
	X6,
	X2,
	X3,
	X5,
	X7);
output 	Y;
input 	X1;
input 	[2:0] S;
input 	X0;
input 	X4;
input 	X6;
input 	X2;
input 	X3;
input 	X5;
input 	X7;

// Design Ports Information
// Y	=>  Location: PIN_11,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X3	=>  Location: PIN_138,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X2	=>  Location: PIN_137,	 I/O Standard: 2.5 V,	 Current Strength: Default
// S[0]	=>  Location: PIN_141,	 I/O Standard: 2.5 V,	 Current Strength: Default
// S[2]	=>  Location: PIN_28,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X1	=>  Location: PIN_10,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X0	=>  Location: PIN_136,	 I/O Standard: 2.5 V,	 Current Strength: Default
// S[1]	=>  Location: PIN_142,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X7	=>  Location: PIN_144,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X6	=>  Location: PIN_2,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X5	=>  Location: PIN_143,	 I/O Standard: 2.5 V,	 Current Strength: Default
// X4	=>  Location: PIN_135,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \Y~output_o ;
wire \X6~input_o ;
wire \S[2]~input_o ;
wire \X7~input_o ;
wire \S[0]~input_o ;
wire \inst3~3_combout ;
wire \X5~input_o ;
wire \X4~input_o ;
wire \inst3~4_combout ;
wire \S[1]~input_o ;
wire \X2~input_o ;
wire \X3~input_o ;
wire \inst3~0_combout ;
wire \X1~input_o ;
wire \X0~input_o ;
wire \inst3~1_combout ;
wire \inst3~2_combout ;
wire \inst3~5_combout ;


hard_block auto_generated_inst(
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// Location: IOOBUF_X0_Y18_N23
cycloneive_io_obuf \Y~output (
	.i(\inst3~5_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\Y~output_o ),
	.obar());
// synopsys translate_off
defparam \Y~output .bus_hold = "false";
defparam \Y~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X0_Y23_N8
cycloneive_io_ibuf \X6~input (
	.i(X6),
	.ibar(gnd),
	.o(\X6~input_o ));
// synopsys translate_off
defparam \X6~input .bus_hold = "false";
defparam \X6~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X0_Y9_N8
cycloneive_io_ibuf \S[2]~input (
	.i(S[2]),
	.ibar(gnd),
	.o(\S[2]~input_o ));
// synopsys translate_off
defparam \S[2]~input .bus_hold = "false";
defparam \S[2]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X1_Y24_N8
cycloneive_io_ibuf \X7~input (
	.i(X7),
	.ibar(gnd),
	.o(\X7~input_o ));
// synopsys translate_off
defparam \X7~input .bus_hold = "false";
defparam \X7~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X5_Y24_N8
cycloneive_io_ibuf \S[0]~input (
	.i(S[0]),
	.ibar(gnd),
	.o(\S[0]~input_o ));
// synopsys translate_off
defparam \S[0]~input .bus_hold = "false";
defparam \S[0]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X5_Y20_N6
cycloneive_lcell_comb \inst3~3 (
// Equation(s):
// \inst3~3_combout  = (\S[2]~input_o  & ((\S[0]~input_o  & ((\X7~input_o ))) # (!\S[0]~input_o  & (\X6~input_o ))))

	.dataa(\X6~input_o ),
	.datab(\S[2]~input_o ),
	.datac(\X7~input_o ),
	.datad(\S[0]~input_o ),
	.cin(gnd),
	.combout(\inst3~3_combout ),
	.cout());
// synopsys translate_off
defparam \inst3~3 .lut_mask = 16'hC088;
defparam \inst3~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X1_Y24_N1
cycloneive_io_ibuf \X5~input (
	.i(X5),
	.ibar(gnd),
	.o(\X5~input_o ));
// synopsys translate_off
defparam \X5~input .bus_hold = "false";
defparam \X5~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X11_Y24_N15
cycloneive_io_ibuf \X4~input (
	.i(X4),
	.ibar(gnd),
	.o(\X4~input_o ));
// synopsys translate_off
defparam \X4~input .bus_hold = "false";
defparam \X4~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X5_Y20_N0
cycloneive_lcell_comb \inst3~4 (
// Equation(s):
// \inst3~4_combout  = (\S[2]~input_o  & ((\S[0]~input_o  & (\X5~input_o )) # (!\S[0]~input_o  & ((\X4~input_o )))))

	.dataa(\X5~input_o ),
	.datab(\X4~input_o ),
	.datac(\S[2]~input_o ),
	.datad(\S[0]~input_o ),
	.cin(gnd),
	.combout(\inst3~4_combout ),
	.cout());
// synopsys translate_off
defparam \inst3~4 .lut_mask = 16'hA0C0;
defparam \inst3~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X3_Y24_N22
cycloneive_io_ibuf \S[1]~input (
	.i(S[1]),
	.ibar(gnd),
	.o(\S[1]~input_o ));
// synopsys translate_off
defparam \S[1]~input .bus_hold = "false";
defparam \S[1]~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X7_Y24_N1
cycloneive_io_ibuf \X2~input (
	.i(X2),
	.ibar(gnd),
	.o(\X2~input_o ));
// synopsys translate_off
defparam \X2~input .bus_hold = "false";
defparam \X2~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X7_Y24_N8
cycloneive_io_ibuf \X3~input (
	.i(X3),
	.ibar(gnd),
	.o(\X3~input_o ));
// synopsys translate_off
defparam \X3~input .bus_hold = "false";
defparam \X3~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X5_Y20_N24
cycloneive_lcell_comb \inst3~0 (
// Equation(s):
// \inst3~0_combout  = (!\S[2]~input_o  & ((\S[0]~input_o  & ((\X3~input_o ))) # (!\S[0]~input_o  & (\X2~input_o ))))

	.dataa(\S[0]~input_o ),
	.datab(\X2~input_o ),
	.datac(\S[2]~input_o ),
	.datad(\X3~input_o ),
	.cin(gnd),
	.combout(\inst3~0_combout ),
	.cout());
// synopsys translate_off
defparam \inst3~0 .lut_mask = 16'h0E04;
defparam \inst3~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X0_Y18_N15
cycloneive_io_ibuf \X1~input (
	.i(X1),
	.ibar(gnd),
	.o(\X1~input_o ));
// synopsys translate_off
defparam \X1~input .bus_hold = "false";
defparam \X1~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X9_Y24_N8
cycloneive_io_ibuf \X0~input (
	.i(X0),
	.ibar(gnd),
	.o(\X0~input_o ));
// synopsys translate_off
defparam \X0~input .bus_hold = "false";
defparam \X0~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X5_Y20_N10
cycloneive_lcell_comb \inst3~1 (
// Equation(s):
// \inst3~1_combout  = (!\S[2]~input_o  & ((\S[0]~input_o  & (\X1~input_o )) # (!\S[0]~input_o  & ((\X0~input_o )))))

	.dataa(\S[0]~input_o ),
	.datab(\X1~input_o ),
	.datac(\S[2]~input_o ),
	.datad(\X0~input_o ),
	.cin(gnd),
	.combout(\inst3~1_combout ),
	.cout());
// synopsys translate_off
defparam \inst3~1 .lut_mask = 16'h0D08;
defparam \inst3~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X5_Y20_N28
cycloneive_lcell_comb \inst3~2 (
// Equation(s):
// \inst3~2_combout  = (\S[1]~input_o  & (\inst3~0_combout )) # (!\S[1]~input_o  & ((\inst3~1_combout )))

	.dataa(gnd),
	.datab(\inst3~0_combout ),
	.datac(\S[1]~input_o ),
	.datad(\inst3~1_combout ),
	.cin(gnd),
	.combout(\inst3~2_combout ),
	.cout());
// synopsys translate_off
defparam \inst3~2 .lut_mask = 16'hCFC0;
defparam \inst3~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X5_Y20_N26
cycloneive_lcell_comb \inst3~5 (
// Equation(s):
// \inst3~5_combout  = (\inst3~2_combout ) # ((\S[1]~input_o  & (\inst3~3_combout )) # (!\S[1]~input_o  & ((\inst3~4_combout ))))

	.dataa(\inst3~3_combout ),
	.datab(\inst3~4_combout ),
	.datac(\S[1]~input_o ),
	.datad(\inst3~2_combout ),
	.cin(gnd),
	.combout(\inst3~5_combout ),
	.cout());
// synopsys translate_off
defparam \inst3~5 .lut_mask = 16'hFFAC;
defparam \inst3~5 .sum_lutc_input = "datac";
// synopsys translate_on

assign Y = \Y~output_o ;

endmodule

module hard_block (

	devpor,
	devclrn,
	devoe);

// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_101,	 I/O Standard: 2.5 V,	 Current Strength: 8mA

input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

wire \~ALTERA_ASDO_DATA1~~padout ;
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
wire \~ALTERA_DATA0~~padout ;
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
wire \~ALTERA_DATA0~~ibuf_o ;


endmodule