154 lines
2.7 KiB
Plaintext
154 lines
2.7 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("inPort0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("inPort1")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("outPort")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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TRANSITION_LIST("inPort0")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 40.0;
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LEVEL 1 FOR 180.0;
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LEVEL 0 FOR 220.0;
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LEVEL 1 FOR 220.0;
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LEVEL 0 FOR 120.0;
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LEVEL 1 FOR 120.0;
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LEVEL 0 FOR 100.0;
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}
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}
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}
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TRANSITION_LIST("inPort1")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 280.0;
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LEVEL 1 FOR 80.0;
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LEVEL 0 FOR 140.0;
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LEVEL 1 FOR 120.0;
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LEVEL 0 FOR 100.0;
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LEVEL 1 FOR 220.0;
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LEVEL 0 FOR 60.0;
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}
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}
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}
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TRANSITION_LIST("outPort")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 500.0;
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LEVEL 1 FOR 120.0;
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LEVEL 0 FOR 160.0;
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LEVEL 1 FOR 120.0;
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LEVEL 0 FOR 100.0;
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}
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "inPort0";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 0;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "inPort1";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "outPort";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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TREE_LEVEL = 0;
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}
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TIME_BAR
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{
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TIME = 0;
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MASTER = TRUE;
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}
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;
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