93 lines
2.4 KiB
Plaintext
93 lines
2.4 KiB
Plaintext
// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// *****************************************************************************
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// This file contains a Verilog test bench with test vectors .The test vectors
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// are exported from a vector file in the Quartus Waveform Editor and apply to
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// the top level entity of the current Quartus project .The user can use this
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// testbench to simulate his design using a third-party simulation tool .
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// *****************************************************************************
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// Generated on "11/04/2022 15:15:39"
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// Verilog Test Bench (with test vectors) for design : Dec2_4
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//
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// Simulation tool : 3rd Party
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//
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`timescale 1 ps/ 1 ps
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module Dec2_4_vlg_vec_tst();
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// constants
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// general purpose registers
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reg E0L;
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reg E1;
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reg X0;
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reg X1;
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// wires
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wire Y0;
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wire Y1;
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wire Y2;
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wire Y3;
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// assign statements (if any)
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Dec2_4 i1 (
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// port map - connection between master ports and signals/registers
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.E0L(E0L),
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.E1(E1),
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.X0(X0),
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.X1(X1),
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.Y0(Y0),
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.Y1(Y1),
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.Y2(Y2),
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.Y3(Y3)
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);
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initial
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begin
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#1000000 $finish;
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end
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// E0L
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always
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begin
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E0L = 1'b0;
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E0L = #100000 1'b1;
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#100000;
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end
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// E1
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always
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begin
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E1 = 1'b0;
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E1 = #50000 1'b1;
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#50000;
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end
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// X1
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always
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begin
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X1 = 1'b0;
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X1 = #25000 1'b1;
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#25000;
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end
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// X0
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always
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begin
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X0 = 1'b0;
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X0 = #12500 1'b1;
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#12500;
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end
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endmodule
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