144 lines
3.7 KiB
VHDL
144 lines
3.7 KiB
VHDL
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- *****************************************************************************
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-- This file contains a Vhdl test bench with test vectors .The test vectors
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-- are exported from a vector file in the Quartus Waveform Editor and apply to
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-- the top level entity of the current Quartus project .The user can use this
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-- testbench to simulate his design using a third-party simulation tool .
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-- *****************************************************************************
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-- Generated on "03/07/2023 20:57:57"
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-- Vhdl Test Bench(with test vectors) for design : EqCmpDemo
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--
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-- Simulation tool : 3rd Party
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY EqCmpDemo_vhd_vec_tst IS
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END EqCmpDemo_vhd_vec_tst;
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ARCHITECTURE EqCmpDemo_arch OF EqCmpDemo_vhd_vec_tst IS
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-- constants
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-- signals
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SIGNAL LEDG : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL SW : STD_LOGIC_VECTOR(7 DOWNTO 0);
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COMPONENT EqCmpDemo
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PORT (
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LEDG : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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i1 : EqCmpDemo
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PORT MAP (
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-- list connections between master ports and signals
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LEDG => LEDG,
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SW => SW
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);
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-- SW[7]
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t_prcs_SW_7: PROCESS
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BEGIN
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SW(7) <= '0';
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WAIT FOR 400000 ps;
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SW(7) <= '1';
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WAIT FOR 400000 ps;
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SW(7) <= '0';
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WAIT;
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END PROCESS t_prcs_SW_7;
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-- SW[6]
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t_prcs_SW_6: PROCESS
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BEGIN
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FOR i IN 1 TO 2
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LOOP
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SW(6) <= '0';
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WAIT FOR 200000 ps;
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SW(6) <= '1';
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WAIT FOR 200000 ps;
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END LOOP;
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SW(6) <= '0';
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WAIT;
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END PROCESS t_prcs_SW_6;
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-- SW[5]
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t_prcs_SW_5: PROCESS
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BEGIN
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LOOP
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SW(5) <= '0';
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WAIT FOR 100000 ps;
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SW(5) <= '1';
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WAIT FOR 100000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_SW_5;
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-- SW[4]
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t_prcs_SW_4: PROCESS
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BEGIN
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LOOP
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SW(4) <= '0';
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WAIT FOR 50000 ps;
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SW(4) <= '1';
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WAIT FOR 50000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_SW_4;
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-- SW[3]
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t_prcs_SW_3: PROCESS
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BEGIN
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LOOP
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SW(3) <= '0';
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WAIT FOR 25000 ps;
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SW(3) <= '1';
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WAIT FOR 25000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_SW_3;
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-- SW[2]
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t_prcs_SW_2: PROCESS
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BEGIN
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LOOP
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SW(2) <= '0';
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WAIT FOR 12500 ps;
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SW(2) <= '1';
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WAIT FOR 12500 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_SW_2;
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-- SW[1]
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t_prcs_SW_1: PROCESS
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BEGIN
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LOOP
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SW(1) <= '0';
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WAIT FOR 6250 ps;
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SW(1) <= '1';
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WAIT FOR 6250 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_SW_1;
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-- SW[0]
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t_prcs_SW_0: PROCESS
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BEGIN
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FOR i IN 1 TO 148
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LOOP
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SW(0) <= '0';
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WAIT FOR 3375 ps;
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SW(0) <= '1';
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WAIT FOR 3375 ps;
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END LOOP;
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SW(0) <= '0';
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WAIT;
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END PROCESS t_prcs_SW_0;
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END EqCmpDemo_arch;
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