24 lines
432 B
VHDL
24 lines
432 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Register8 is
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port
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(
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dataIn : in std_logic_vector(7 downto 0);
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clk : in std_logic;
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wrEn : in std_logic;
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dataOut : out std_logic_vector(7 downto 0)
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);
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end Register8;
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architecture Behavioral of Register8 is
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begin
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process (clk)
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begin
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if (rising_edge(clk)) then
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if (wrEn = '1') then
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dataOut <= dataIn;
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end if;
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end if;
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end process;
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end Behavioral; |