30 lines
595 B
VHDL
30 lines
595 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity ClkEnableGenerator is
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port(clkIn4Hz : in std_logic;
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mode : in std_logic;
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clkEnable : out std_logic;
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tick1Hz : out std_logic);
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end ClkEnableGenerator;
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architecture RTL of ClkEnableGenerator is
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signal s_counter : unsigned(1 downto 0);
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begin
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process(clkIn4Hz)
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begin
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if (rising_edge(clkIn4Hz)) then
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s_counter <= s_counter + 1;
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end if;
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end process;
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clkEnable <= '1' when (mode ='1') else
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'1' when (mode ='0') and (s_counter = "00") else
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'0';
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tick1Hz <= s_counter(1);
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end RTL;
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