53 lines
1.1 KiB
VHDL
53 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity TimerModule is
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port
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(
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clock : in std_logic;
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reset : in std_logic;
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timerEnable : in std_logic;
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timerNew : in std_logic;
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timerValue : in std_logic_vector(6 downto 0);
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timerOut : out std_logic_vector(6 downto 0)
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);
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end TimerModule;
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architecture Behavioral of TimerModule is
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signal s_clock, s_reset, s_pulse : std_logic;
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signal s_count : unsigned(6 downto 0);
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begin
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s_clock <= clock;
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s_reset <= reset;
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pulse_gen : entity work.PulseGen(Behavioral)
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generic map (MAX => 50_000_000)
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port map
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(
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clock => s_clock,
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reset => s_reset,
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pulse => s_pulse
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);
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process(s_clock, timerNew, timerEnable)
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begin
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if (rising_edge(s_clock)) then
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if (s_reset = '1') then
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s_count <= unsigned(timerValue);
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else
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if ( timerNew = '1' ) then
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s_count <= unsigned(timerValue);
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else
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if ( s_pulse = '1' and timerEnable = '1' and s_count > 0 ) then
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s_count <= s_count - 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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timerOut <= std_logic_vector(s_count);
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end Behavioral; |