uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript

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# do LogicDemo.do
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 20:45:47 on Mar 07,2023
# vcom -work work LogicTop.vho
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package cycloneive_atom_pack
# -- Loading package cycloneive_components
# -- Compiling entity hard_block
# -- Compiling architecture structure of hard_block
# -- Compiling entity LogicTop
# -- Compiling architecture structure of LogicTop
# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 20:45:47 on Mar 07,2023
# vcom -work work LogicUnit.vwf.vht
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity LogicTop_vhd_vec_tst
# -- Compiling architecture LogicTop_arch of LogicTop_vhd_vec_tst
# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
# Start time: 20:45:47 on Mar 07,2023
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.logictop_vhd_vec_tst(logictop_arch)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading cycloneive.cycloneive_atom_pack(body)
# Loading cycloneive.cycloneive_components
# Loading work.logictop(structure)
# Loading work.hard_block(structure)
# Loading ieee.std_logic_arith(body)
# Loading cycloneive.cycloneive_io_obuf(arch)
# Loading cycloneive.cycloneive_io_ibuf(arch)
# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
# after#31
# End time: 20:45:48 on Mar 07,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0