136 lines
9.3 KiB
Plaintext
136 lines
9.3 KiB
Plaintext
Flow report for AND2Gate
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Wed Mar 1 12:11:29 2023
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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6. Flow OS Summary
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7. Flow Log
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8. Flow Messages
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9. Flow Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Flow Summary ;
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+------------------------------------+---------------------------------------------+
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; Flow Status ; Successful - Wed Mar 1 12:11:29 2023 ;
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; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
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; Revision Name ; AND2Gate ;
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; Top-level Entity Name ; GateDemo ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE115F29C7 ;
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; Timing Models ; Final ;
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; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
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; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
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; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
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; Total registers ; 0 ;
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; Total pins ; 4 / 529 ( < 1 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
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; Total PLLs ; 0 / 4 ( 0 % ) ;
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+------------------------------------+---------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 03/01/2023 12:10:48 ;
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; Main task ; Compilation ;
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; Revision Name ; AND2Gate ;
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+-------------------+---------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
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; COMPILER_SIGNATURE_ID ; 198516037997543.167767264809108 ; -- ; -- ; -- ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
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; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
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; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; TOP_LEVEL_ENTITY ; GateDemo ; AND2Gate ; -- ; -- ;
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+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 431 MB ; 00:00:33 ;
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; Fitter ; 00:00:15 ; 1.0 ; 1153 MB ; 00:00:23 ;
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; Assembler ; 00:00:05 ; 1.0 ; 366 MB ; 00:00:05 ;
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; Timing Analyzer ; 00:00:03 ; 1.0 ; 535 MB ; 00:00:03 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:01 ;
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; Total ; 00:00:37 ; -- ; -- ; 00:01:05 ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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+----------------------------------------------------------------------------------------+
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; Flow OS Summary ;
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+----------------------+------------------+----------------+------------+----------------+
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; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
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+----------------------+------------------+----------------+------------+----------------+
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; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
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; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
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; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
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; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
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; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
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+----------------------+------------------+----------------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate
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quartus_fit --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
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quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
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quartus_sta VHDLDemo -c AND2Gate
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quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
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