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uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/db/MuxDemo.fit.qmsg

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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678382521345 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678382521345 ""}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "MuxDemo EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design MuxDemo" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1678382521435 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1678382521479 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1678382521479 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678382521552 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678382521556 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "LEDG\[8\] PIN_F17 " "Can't place node \"LEDG\[8\]\" -- illegal location assignment PIN_F17" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { LEDG[8] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 96 592 768 112 "LEDG" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 22 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[10\] PIN_AC24 " "Can't place node \"SW\[10\]\" -- illegal location assignment PIN_AC24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[10] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 32 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[1\] PIN_M21 " "Can't place node \"KEY\[1\]\" -- illegal location assignment PIN_M21" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 25 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[9\] PIN_AB25 " "Can't place node \"SW\[9\]\" -- illegal location assignment PIN_AB25" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[9] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[0\] PIN_M23 " "Can't place node \"KEY\[0\]\" -- illegal location assignment PIN_M23" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 26 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[8\] PIN_AC25 " "Can't place node \"SW\[8\]\" -- illegal location assignment PIN_AC25" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[8] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 34 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[11\] PIN_AB24 " "Can't place node \"SW\[11\]\" -- illegal location assignment PIN_AB24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[11] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[3\] PIN_R24 " "Can't place node \"KEY\[3\]\" -- illegal location assignment PIN_R24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 23 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[5\] PIN_AC26 " "Can't place node \"SW\[5\]\" -- illegal location assignment PIN_AC26" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 37 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[6\] PIN_AD26 " "Can't place node \"SW\[6\]\" -- illegal location assignment PIN_AD26" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 36 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[4\] PIN_AB27 " "Can't place node \"SW\[4\]\" -- illegal location assignment PIN_AB27" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 38 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[7\] PIN_AB26 " "Can't place node \"SW\[7\]\" -- illegal location assignment PIN_AB26" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "KEY\[2\] PIN_N21 " "Can't place node \"KEY\[2\]\" -- illegal location assignment PIN_N21" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { KEY[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 112 312 480 128 "KEY" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 24 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[2\] PIN_AC27 " "Can't place node \"SW\[2\]\" -- illegal location assignment PIN_AC27" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 40 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521583 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[1\] PIN_AC28 " "Can't place node \"SW\[1\]\" -- illegal location assignment PIN_AC28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 41 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[0\] PIN_AB28 " "Can't place node \"SW\[0\]\" -- illegal location assignment PIN_AB28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 42 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[3\] PIN_AD27 " "Can't place node \"SW\[3\]\" -- illegal location assignment PIN_AD27" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 39 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[13\] PIN_AA24 " "Can't place node \"SW\[13\]\" -- illegal location assignment PIN_AA24" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[13] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[14\] PIN_AA23 " "Can't place node \"SW\[14\]\" -- illegal location assignment PIN_AA23" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[14] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 28 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[12\] PIN_AB23 " "Can't place node \"SW\[12\]\" -- illegal location assignment PIN_AB23" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[12] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 30 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Error" "EFITCC_FITCC_ILLEGAL_LOCATION_ASSIGNMENT" "SW\[15\] PIN_AA22 " "Can't place node \"SW\[15\]\" -- illegal location assignment PIN_AA22" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[15] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 128 312 480 144 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 171016 "Can't place node \"%1!s!\" -- illegal location assignment %2!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678382521584 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678382521597 ""}
{ "Error" "EFITCC_FITCC_FAIL" "" "Can't fit design in device" { } { } 0 171000 "Can't fit design in device" 0 0 "Fitter" 0 -1 1678382521597 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Fitter 22 s 3 s Quartus Prime " "Quartus Prime Fitter was unsuccessful. 22 errors, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "386 " "Peak virtual memory: 386 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678382521619 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Mar 9 17:22:01 2023 " "Processing ended: Thu Mar 9 17:22:01 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678382521619 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678382521619 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678382521619 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678382521619 ""}
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