79 lines
1.6 KiB
VHDL
79 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity DisplaysManager is
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port
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(
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bin_delay : in std_logic_vector(6 downto 0);
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bin_total : in std_logic_vector(6 downto 0);
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bin_extra : in std_logic_vector(3 downto 0);
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D_HEX2 : out std_logic_vector(6 downto 0);
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D_HEX3 : out std_logic_vector(6 downto 0);
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D_HEX4 : out std_logic_vector(6 downto 0);
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D_HEX6 : out std_logic_vector(6 downto 0);
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D_HEX7 : out std_logic_vector(6 downto 0)
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);
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end DisplaysManager;
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architecture Behavioral of DisplaysManager is
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signal s_display2, s_display3, s_display6, s_display7 : std_logic_vector(3 downto 0);
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begin
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binToDec_delay : entity work.BinToDec(Behavioral)
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port map
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(
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binIn => bin_delay,
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decOut0 => s_display6,
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decOut1 => s_display7
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);
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display6 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => s_display6,
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enable => '1',
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decOut_n => D_HEX6
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);
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display7 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => s_display7,
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enable => '1',
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decOut_n => D_HEX7
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);
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binToDec_normal : entity work.BinToDec(Behavioral)
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port map
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(
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binIn => bin_total,
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decOut0 => s_display2,
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decOut1 => s_display3
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);
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display2 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => s_display2,
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enable => '1',
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decOut_n => D_HEX2
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);
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display3 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => s_display3,
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enable => '1',
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decOut_n => D_HEX3
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);
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extra_time_display : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => bin_extra,
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enable => '1',
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decOut_n => D_HEX4
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);
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end Behavioral; |