TiagoRG
/
uaveiro-leci
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4EnDemo.sft

2 lines
39 B
Plaintext
Raw Blame History

set tool_name "ModelSim-Altera (VHDL)"
Reference in New Issue View Git Blame Copy Permalink