291 lines
22 KiB
Plaintext
291 lines
22 KiB
Plaintext
Analysis & Synthesis report for Dec2_4EnDemo
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Wed Mar 1 12:46:25 2023
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. General Register Statistics
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9. Post-Synthesis Netlist Statistics for Top Partition
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10. Elapsed Time Per Partition
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11. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+---------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Wed Mar 1 12:46:25 2023 ;
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; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
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; Revision Name ; Dec2_4EnDemo ;
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; Top-level Entity Name ; Dec2_4EnDemo ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; 4 ;
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; Total combinational functions ; 4 ;
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; Dedicated logic registers ; 0 ;
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; Total registers ; 0 ;
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; Total pins ; 7 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Total PLLs ; 0 ;
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+------------------------------------+---------------------------------------------+
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+------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Device ; EP4CE115F29C7 ; ;
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; Top-level entity name ; Dec2_4EnDemo ; Dec2_4EnDemo ;
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; Family name ; Cyclone IV E ; Cyclone V ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto RAM Block Balancing ; On ; On ;
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; Auto RAM to Logic Cell Conversion ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 2 ; 2 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Resource Aware Inference For Block RAM ; On ; On ;
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+------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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+----------------------------+-------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
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+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
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; Dec2_4En.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd ; ;
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; Dec2_4EnDemo.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd ; ;
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+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
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+-----------------------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+---------------------------------------------+-------------+
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; Resource ; Usage ;
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+---------------------------------------------+-------------+
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; Estimated Total logic elements ; 4 ;
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; ; ;
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; Total combinational functions ; 4 ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 0 ;
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; -- 3 input functions ; 4 ;
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; -- <=2 input functions ; 0 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 4 ;
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; -- arithmetic mode ; 0 ;
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; ; ;
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; Total registers ; 0 ;
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; -- Dedicated logic registers ; 0 ;
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; -- I/O registers ; 0 ;
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; ; ;
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; I/O pins ; 7 ;
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; ; ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; ; ;
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; Maximum fan-out node ; SW[2]~input ;
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; Maximum fan-out ; 4 ;
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; Total fan-out ; 23 ;
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; Average fan-out ; 1.28 ;
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+---------------------------------------------+-------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+--------------+
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; |Dec2_4EnDemo ; 4 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |Dec2_4EnDemo ; Dec2_4EnDemo ; work ;
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; |Dec2_4En:system_core| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Dec2_4EnDemo|Dec2_4En:system_core ; Dec2_4En ; work ;
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+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------+--------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+------------------------------------------------------+
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; General Register Statistics ;
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+----------------------------------------------+-------+
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; Statistic ; Value ;
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+----------------------------------------------+-------+
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; Total registers ; 0 ;
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; Number of registers using Synchronous Clear ; 0 ;
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; Number of registers using Synchronous Load ; 0 ;
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; Number of registers using Asynchronous Clear ; 0 ;
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; Number of registers using Asynchronous Load ; 0 ;
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; Number of registers using Clock Enable ; 0 ;
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; Number of registers using Preset ; 0 ;
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+----------------------------------------------+-------+
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+-----------------------------------------------------+
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; Post-Synthesis Netlist Statistics for Top Partition ;
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+-----------------------+-----------------------------+
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; Type ; Count ;
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+-----------------------+-----------------------------+
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; boundary_port ; 7 ;
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; cycloneiii_lcell_comb ; 4 ;
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; normal ; 4 ;
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; 3 data inputs ; 4 ;
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; ; ;
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; Max LUT depth ; 1.00 ;
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; Average LUT depth ; 1.00 ;
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+-----------------------+-----------------------------+
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+-------------------------------+
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; Elapsed Time Per Partition ;
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+----------------+--------------+
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; Partition Name ; Elapsed Time ;
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+----------------+--------------+
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; Top ; 00:00:00 ;
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+----------------+--------------+
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Analysis & Synthesis
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Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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Info: Processing started: Wed Mar 1 12:46:20 2023
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
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Info (12021): Found 4 design units, including 1 entities, in source file Dec2_4En.vhd
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Info (12022): Found design unit 1: Dec2_4En-BehavEquations File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 12
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Info (12022): Found design unit 2: Dec2_4En-BehavAssign File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 20
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Info (12022): Found design unit 3: Dec2_4En-BehavProc File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 29
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Info (12023): Found entity 1: Dec2_4En File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd Line: 4
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Info (12021): Found 2 design units, including 1 entities, in source file Dec2_4EnDemo.vhd
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Info (12022): Found design unit 1: Dec2_4EnDemo-Shell File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd Line: 12
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Info (12023): Found entity 1: Dec2_4EnDemo File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd Line: 4
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Info (12127): Elaborating entity "Dec2_4EnDemo" for the top level hierarchy
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Info (12129): Elaborating entity "Dec2_4En" using architecture "A:behavproc" for hierarchy "Dec2_4En:system_core" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd Line: 14
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Info (286030): Timing-Driven Synthesis is running
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Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
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Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
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Info (21057): Implemented 11 device resources after synthesis - the final resource count might be different
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Info (21058): Implemented 3 input pins
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Info (21059): Implemented 4 output pins
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Info (21061): Implemented 4 logic cells
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Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 429 megabytes
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Info: Processing ended: Wed Mar 1 12:46:25 2023
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Info: Elapsed time: 00:00:05
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Info: Total CPU time (on all processors): 00:00:12
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