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uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.map.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678380679758 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678380679758 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 16:51:19 2023 " "Processing started: Thu Mar 9 16:51:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678380679758 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380679758 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380679758 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678380679908 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678380679908 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FullAdder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FullAdder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FullAdder-Behavioral " "Found design unit 1: FullAdder-Behavioral" { } { { "FullAdder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} { "Info" "ISGN_ENTITY_NAME" "1 FullAdder " "Found entity 1: FullAdder" { } { { "FullAdder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685473 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adder4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Adder4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Adder4-Structural " "Found design unit 1: Adder4-Structural" { } { { "Adder4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} { "Info" "ISGN_ENTITY_NAME" "1 Adder4 " "Found entity 1: Adder4" { } { { "Adder4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685473 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AdderDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AdderDemo " "Found entity 1: AdderDemo" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685473 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AddSub4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AddSub4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AddSub4-Behavioral " "Found design unit 1: AddSub4-Behavioral" { } { { "AddSub4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd" 29 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685474 ""} { "Info" "ISGN_ENTITY_NAME" "1 AddSub4 " "Found entity 1: AddSub4" { } { { "AddSub4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678380685474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380685474 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "AdderDemo " "Elaborating entity \"AdderDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678380685504 ""}
{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND Ground2 " "Primitive \"GND\" of instance \"Ground2\" not used" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 304 464 496 336 "Ground2" "" } } } } } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Analysis & Synthesis" 0 -1 1678380685505 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Adder4 Adder4:Adder4Demo " "Elaborating entity \"Adder4\" for hierarchy \"Adder4:Adder4Demo\"" { } { { "AdderDemo.bdf" "Adder4Demo" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 160 488 640 272 "Adder4Demo" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380685506 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "FullAdder Adder4:Adder4Demo\|FullAdder:bit0 A:behavioral " "Elaborating entity \"FullAdder\" using architecture \"A:behavioral\" for hierarchy \"Adder4:Adder4Demo\|FullAdder:bit0\"" { } { { "Adder4.vhd" "bit0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd" 17 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380685507 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AddSub4 AddSub4:AddSub4Demo " "Elaborating entity \"AddSub4\" for hierarchy \"AddSub4:AddSub4Demo\"" { } { { "AdderDemo.bdf" "AddSub4Demo" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 344 488 640 456 "AddSub4Demo" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380685509 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 184 648 824 200 "LEDR\[3..0\]" "" } { 368 648 824 384 "LEDR\[13..10\]" "" } { 384 648 824 400 "LEDR\[14\]" "" } { 200 648 824 216 "LEDR\[4\]" "" } { 288 488 664 304 "LEDR\[9..5\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678380685841 "|AdderDemo|LEDR[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678380685841 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678380685896 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678380686259 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678380686259 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 200 312 480 216 "SW" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678380686280 "|AdderDemo|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf" { { 200 312 480 216 "SW" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678380686280 "|AdderDemo|SW[8]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678380686280 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "51 " "Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Implemented 19 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678380686280 ""} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Implemented 15 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678380686280 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17 " "Implemented 17 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678380686280 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678380686280 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678380686284 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 16:51:26 2023 " "Processing ended: Thu Mar 9 16:51:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678380686284 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678380686284 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678380686284 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678380686284 ""}
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