294 lines
8.2 KiB
VHDL
294 lines
8.2 KiB
VHDL
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
|
|
-- Your use of Intel Corporation's design tools, logic functions
|
|
-- and other software and tools, and any partner logic
|
|
-- functions, and any output files from any of the foregoing
|
|
-- (including device programming or simulation files), and any
|
|
-- associated documentation or information are expressly subject
|
|
-- to the terms and conditions of the Intel Program License
|
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
|
-- agreement, including, without limitation, that your use is for
|
|
-- the sole purpose of programming logic devices manufactured by
|
|
-- Intel and sold by Intel or its authorized distributors. Please
|
|
-- refer to the applicable agreement for further details, at
|
|
-- https://fpgasoftware.intel.com/eula.
|
|
|
|
-- VENDOR "Altera"
|
|
-- PROGRAM "Quartus Prime"
|
|
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
|
|
|
-- DATE "03/01/2023 12:46:36"
|
|
|
|
--
|
|
-- Device: Altera EP4CE115F29C7 Package FBGA780
|
|
--
|
|
|
|
--
|
|
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
|
|
--
|
|
|
|
LIBRARY CYCLONEIVE;
|
|
LIBRARY IEEE;
|
|
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
ENTITY hard_block IS
|
|
PORT (
|
|
devoe : IN std_logic;
|
|
devclrn : IN std_logic;
|
|
devpor : IN std_logic
|
|
);
|
|
END hard_block;
|
|
|
|
-- Design Ports Information
|
|
-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
|
|
|
|
|
|
ARCHITECTURE structure OF hard_block IS
|
|
SIGNAL gnd : std_logic := '0';
|
|
SIGNAL vcc : std_logic := '1';
|
|
SIGNAL unknown : std_logic := 'X';
|
|
SIGNAL ww_devoe : std_logic;
|
|
SIGNAL ww_devclrn : std_logic;
|
|
SIGNAL ww_devpor : std_logic;
|
|
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
|
|
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
|
|
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
|
|
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
|
|
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
|
|
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
|
|
|
|
BEGIN
|
|
|
|
ww_devoe <= devoe;
|
|
ww_devclrn <= devclrn;
|
|
ww_devpor <= devpor;
|
|
END structure;
|
|
|
|
|
|
LIBRARY CYCLONEIVE;
|
|
LIBRARY IEEE;
|
|
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
ENTITY Dec2_4EnDemo IS
|
|
PORT (
|
|
SW : IN std_logic_vector(2 DOWNTO 0);
|
|
LEDR : OUT std_logic_vector(3 DOWNTO 0)
|
|
);
|
|
END Dec2_4EnDemo;
|
|
|
|
-- Design Ports Information
|
|
-- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
|
|
-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
|
|
|
|
|
|
ARCHITECTURE structure OF Dec2_4EnDemo IS
|
|
SIGNAL gnd : std_logic := '0';
|
|
SIGNAL vcc : std_logic := '1';
|
|
SIGNAL unknown : std_logic := 'X';
|
|
SIGNAL devoe : std_logic := '1';
|
|
SIGNAL devclrn : std_logic := '1';
|
|
SIGNAL devpor : std_logic := '1';
|
|
SIGNAL ww_devoe : std_logic;
|
|
SIGNAL ww_devclrn : std_logic;
|
|
SIGNAL ww_devpor : std_logic;
|
|
SIGNAL ww_SW : std_logic_vector(2 DOWNTO 0);
|
|
SIGNAL ww_LEDR : std_logic_vector(3 DOWNTO 0);
|
|
SIGNAL \LEDR[0]~output_o\ : std_logic;
|
|
SIGNAL \LEDR[1]~output_o\ : std_logic;
|
|
SIGNAL \LEDR[2]~output_o\ : std_logic;
|
|
SIGNAL \LEDR[3]~output_o\ : std_logic;
|
|
SIGNAL \SW[1]~input_o\ : std_logic;
|
|
SIGNAL \SW[2]~input_o\ : std_logic;
|
|
SIGNAL \SW[0]~input_o\ : std_logic;
|
|
SIGNAL \system_core|outputs[0]~0_combout\ : std_logic;
|
|
SIGNAL \system_core|outputs[1]~1_combout\ : std_logic;
|
|
SIGNAL \system_core|outputs[2]~2_combout\ : std_logic;
|
|
SIGNAL \system_core|outputs[3]~3_combout\ : std_logic;
|
|
|
|
COMPONENT hard_block
|
|
PORT (
|
|
devoe : IN std_logic;
|
|
devclrn : IN std_logic;
|
|
devpor : IN std_logic);
|
|
END COMPONENT;
|
|
|
|
BEGIN
|
|
|
|
ww_SW <= SW;
|
|
LEDR <= ww_LEDR;
|
|
ww_devoe <= devoe;
|
|
ww_devclrn <= devclrn;
|
|
ww_devpor <= devpor;
|
|
auto_generated_inst : hard_block
|
|
PORT MAP (
|
|
devoe => ww_devoe,
|
|
devclrn => ww_devclrn,
|
|
devpor => ww_devpor);
|
|
|
|
-- Location: IOOBUF_X69_Y73_N16
|
|
\LEDR[0]~output\ : cycloneive_io_obuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
open_drain_output => "false")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => \system_core|outputs[0]~0_combout\,
|
|
devoe => ww_devoe,
|
|
o => \LEDR[0]~output_o\);
|
|
|
|
-- Location: IOOBUF_X94_Y73_N2
|
|
\LEDR[1]~output\ : cycloneive_io_obuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
open_drain_output => "false")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => \system_core|outputs[1]~1_combout\,
|
|
devoe => ww_devoe,
|
|
o => \LEDR[1]~output_o\);
|
|
|
|
-- Location: IOOBUF_X94_Y73_N9
|
|
\LEDR[2]~output\ : cycloneive_io_obuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
open_drain_output => "false")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => \system_core|outputs[2]~2_combout\,
|
|
devoe => ww_devoe,
|
|
o => \LEDR[2]~output_o\);
|
|
|
|
-- Location: IOOBUF_X107_Y73_N16
|
|
\LEDR[3]~output\ : cycloneive_io_obuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
open_drain_output => "false")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => \system_core|outputs[3]~3_combout\,
|
|
devoe => ww_devoe,
|
|
o => \LEDR[3]~output_o\);
|
|
|
|
-- Location: IOIBUF_X115_Y14_N1
|
|
\SW[1]~input\ : cycloneive_io_ibuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
simulate_z_as => "z")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => ww_SW(1),
|
|
o => \SW[1]~input_o\);
|
|
|
|
-- Location: IOIBUF_X115_Y15_N8
|
|
\SW[2]~input\ : cycloneive_io_ibuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
simulate_z_as => "z")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => ww_SW(2),
|
|
o => \SW[2]~input_o\);
|
|
|
|
-- Location: IOIBUF_X115_Y17_N1
|
|
\SW[0]~input\ : cycloneive_io_ibuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
simulate_z_as => "z")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => ww_SW(0),
|
|
o => \SW[0]~input_o\);
|
|
|
|
-- Location: LCCOMB_X107_Y69_N0
|
|
\system_core|outputs[0]~0\ : cycloneive_lcell_comb
|
|
-- Equation(s):
|
|
-- \system_core|outputs[0]~0_combout\ = (!\SW[1]~input_o\ & (\SW[2]~input_o\ & !\SW[0]~input_o\))
|
|
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
lut_mask => "0000000000110000",
|
|
sum_lutc_input => "datac")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
datab => \SW[1]~input_o\,
|
|
datac => \SW[2]~input_o\,
|
|
datad => \SW[0]~input_o\,
|
|
combout => \system_core|outputs[0]~0_combout\);
|
|
|
|
-- Location: LCCOMB_X107_Y69_N2
|
|
\system_core|outputs[1]~1\ : cycloneive_lcell_comb
|
|
-- Equation(s):
|
|
-- \system_core|outputs[1]~1_combout\ = (!\SW[1]~input_o\ & (\SW[2]~input_o\ & \SW[0]~input_o\))
|
|
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
lut_mask => "0011000000000000",
|
|
sum_lutc_input => "datac")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
datab => \SW[1]~input_o\,
|
|
datac => \SW[2]~input_o\,
|
|
datad => \SW[0]~input_o\,
|
|
combout => \system_core|outputs[1]~1_combout\);
|
|
|
|
-- Location: LCCOMB_X107_Y69_N4
|
|
\system_core|outputs[2]~2\ : cycloneive_lcell_comb
|
|
-- Equation(s):
|
|
-- \system_core|outputs[2]~2_combout\ = (\SW[1]~input_o\ & (\SW[2]~input_o\ & !\SW[0]~input_o\))
|
|
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
lut_mask => "0000000011000000",
|
|
sum_lutc_input => "datac")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
datab => \SW[1]~input_o\,
|
|
datac => \SW[2]~input_o\,
|
|
datad => \SW[0]~input_o\,
|
|
combout => \system_core|outputs[2]~2_combout\);
|
|
|
|
-- Location: LCCOMB_X107_Y69_N14
|
|
\system_core|outputs[3]~3\ : cycloneive_lcell_comb
|
|
-- Equation(s):
|
|
-- \system_core|outputs[3]~3_combout\ = (\SW[1]~input_o\ & (\SW[2]~input_o\ & \SW[0]~input_o\))
|
|
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
lut_mask => "1100000000000000",
|
|
sum_lutc_input => "datac")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
datab => \SW[1]~input_o\,
|
|
datac => \SW[2]~input_o\,
|
|
datad => \SW[0]~input_o\,
|
|
combout => \system_core|outputs[3]~3_combout\);
|
|
|
|
ww_LEDR(0) <= \LEDR[0]~output_o\;
|
|
|
|
ww_LEDR(1) <= \LEDR[1]~output_o\;
|
|
|
|
ww_LEDR(2) <= \LEDR[2]~output_o\;
|
|
|
|
ww_LEDR(3) <= \LEDR[3]~output_o\;
|
|
END structure;
|
|
|
|
|