31 lines
706 B
VHDL
31 lines
706 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity RegN is
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generic(size : positive := 8);
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port(asyncReset : in std_logic;
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clk : in std_logic;
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enable : in std_logic;
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syncReset : in std_logic;
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dataIn : in std_logic_vector((size - 1) downto 0);
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dataOut : out std_logic_vector((size - 1) downto 0));
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end RegN;
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architecture Behavioral of RegN is
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begin
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reg_proc : process(asyncReset, clk)
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begin
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if (asyncReset = '1') then
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dataOut <= (others => '0');
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elsif (rising_edge(clk)) then
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if (enable = '1') then
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if (syncReset = '1') then
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dataOut <= (others => '0');
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else
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dataOut <= dataIn;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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