20 lines
1.4 KiB
Plaintext
20 lines
1.4 KiB
Plaintext
vendor_name = ModelSim
|
|
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf
|
|
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd
|
|
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vwf
|
|
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd
|
|
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd
|
|
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd
|
|
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
|
|
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
|
|
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
|
|
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
|
|
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cbx.xml
|
|
design_name = hard_block
|
|
design_name = GateDemo
|
|
instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1
|
|
instance = comp, \LEDR[1]~output\, LEDR[1]~output, GateDemo, 1
|
|
instance = comp, \SW[1]~input\, SW[1]~input, GateDemo, 1
|
|
instance = comp, \SW[0]~input\, SW[0]~input, GateDemo, 1
|
|
instance = comp, \system_core|and_gate|outPort\, system_core|and_gate|outPort, GateDemo, 1
|