TiagoRG 3ea15be20e [LSD] pratica01 part3 simulation waveform created		2023-03-07 20:59:42 +00:00
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work	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
LogicDemo.do	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
LogicDemo.msim.vcd	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
LogicDemo_20230307204548.sim.vwf	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
LogicTop.sft	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
LogicTop.vho	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
LogicTop_modelsim.xrf	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
LogicUnit.vwf.vht	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
transcript	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00
vwf_sim_transcript	[LSD] pratica01 part3 simulation waveform created	2023-03-07 20:59:42 +00:00