50 lines
1.5 KiB
VHDL
50 lines
1.5 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity CombShiftUnit is
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port
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(
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clk : in std_logic;
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dataIn : in std_logic_vector(7 downto 0);
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loadEn, rotate, dirLeft, shArith : in std_logic;
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shAmount : in std_logic_vector(2 downto 0);
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dataOut : out std_logic_vector(7 downto 0)
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);
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end CombShiftUnit;
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architecture Behavioral of CombShiftUnit is
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signal s_shiftReg : std_logic_vector(7 downto 0);
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begin
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process (clk)
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begin
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if (falling_edge(clk)) then
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if (loaden = '1') then
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s_shiftReg <= datain;
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elsif (rotate = '1') then
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if (dirleft = '1') then
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s_shiftReg <= std_logic_vector( rotate_left ( unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) );
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else
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s_shiftReg <= std_logic_vector( rotate_right( unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) );
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end if;
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elsif (sharith = '1') then
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if (dirleft = '1') then
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s_shiftReg <= std_logic_vector( shift_left ( signed(s_shiftReg), to_integer(unsigned(shAmount)) ) );
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else
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s_shiftReg <= std_logic_vector( shift_right( signed(s_shiftReg), to_integer(unsigned(shAmount)) ) );
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end if;
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else
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if (dirleft = '1') then
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s_shiftReg <= std_logic_vector( shift_left ( unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) );
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else
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s_shiftReg <= std_logic_vector( shift_right( unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) );
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end if;
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end if;
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end if;
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end process;
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dataOut <= s_shiftReg;
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end Behavioral; |