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TiagoRG 60947591ac [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
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DisplayDemo [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
DisplayDemoVHDL [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
Mux2_1Demo [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
Mux4_1Demo [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
part1 [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
LSD_2022-22_TrabPrat02.pdf [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00
README.md [LSD] Readded the directory now with the necessary directories only 2023-03-29 00:15:35 +01:00

README.md

Laboratórios de Sistemas Digitais

Trabalho prático 02

Tópico principal da aula: Modelação em VHDL, simulação e implementação de componentes combinatórios

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