7818 lines
26 KiB
Plaintext
7818 lines
26 KiB
Plaintext
$comment
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File created using the following command:
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vcd file MuxDemo.msim.vcd -direction
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$end
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$date
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Fri Nov 18 14:55:38 2022
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$end
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$version
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ModelSim Version 2020.1
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$end
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$timescale
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1ps
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$end
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$scope module mux16_1_vhd_vec_tst $end
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$var wire 1 ! I0 $end
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$var wire 1 " I2 $end
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$var wire 1 # I3 $end
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$var wire 1 $ I4 $end
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$var wire 1 % I5 $end
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$var wire 1 & I6 $end
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$var wire 1 ' I7 $end
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$var wire 1 ( I8 $end
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$var wire 1 ) I9 $end
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$var wire 1 * I10 $end
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$var wire 1 + I11 $end
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$var wire 1 , I12 $end
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$var wire 1 - I13 $end
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$var wire 1 . I14 $end
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$var wire 1 / I15 $end
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$var wire 1 0 pin_name1 $end
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$var wire 1 1 Sel1 $end
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$var wire 1 2 Sel2 $end
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$var wire 1 3 Sel3 $end
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$var wire 1 4 Sel4 $end
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$var wire 1 5 ze $end
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$scope module i1 $end
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$var wire 1 6 gnd $end
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$var wire 1 7 vcc $end
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$var wire 1 8 unknown $end
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$var wire 1 9 devoe $end
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$var wire 1 : devclrn $end
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$var wire 1 ; devpor $end
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$var wire 1 < ww_devoe $end
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$var wire 1 = ww_devclrn $end
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$var wire 1 > ww_devpor $end
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$var wire 1 ? ww_pin_name1 $end
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$var wire 1 @ ww_Sel4 $end
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$var wire 1 A ww_Sel3 $end
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$var wire 1 B ww_Sel2 $end
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$var wire 1 C ww_Sel1 $end
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$var wire 1 D ww_I0 $end
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$var wire 1 E ww_ze $end
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$var wire 1 F ww_I2 $end
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$var wire 1 G ww_I3 $end
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$var wire 1 H ww_I4 $end
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$var wire 1 I ww_I5 $end
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$var wire 1 J ww_I6 $end
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$var wire 1 K ww_I7 $end
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$var wire 1 L ww_I8 $end
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$var wire 1 M ww_I9 $end
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$var wire 1 N ww_I10 $end
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$var wire 1 O ww_I11 $end
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$var wire 1 P ww_I12 $end
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$var wire 1 Q ww_I13 $end
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$var wire 1 R ww_I14 $end
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$var wire 1 S ww_I15 $end
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$var wire 1 T \pin_name1~output_o\ $end
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$var wire 1 U \I14~input_o\ $end
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$var wire 1 V \Sel2~input_o\ $end
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$var wire 1 W \Sel1~input_o\ $end
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$var wire 1 X \I12~input_o\ $end
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$var wire 1 Y \inst14|inst2~7_combout\ $end
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$var wire 1 Z \I13~input_o\ $end
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$var wire 1 [ \I15~input_o\ $end
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$var wire 1 \ \inst14|inst2~8_combout\ $end
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$var wire 1 ] \I5~input_o\ $end
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$var wire 1 ^ \I6~input_o\ $end
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$var wire 1 _ \I4~input_o\ $end
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$var wire 1 ` \inst14|inst2~2_combout\ $end
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$var wire 1 a \I7~input_o\ $end
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$var wire 1 b \inst14|inst2~3_combout\ $end
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$var wire 1 c \Sel4~input_o\ $end
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$var wire 1 d \Sel3~input_o\ $end
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$var wire 1 e \I2~input_o\ $end
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$var wire 1 f \ze~input_o\ $end
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$var wire 1 g \I0~input_o\ $end
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$var wire 1 h \inst14|inst2~4_combout\ $end
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$var wire 1 i \I3~input_o\ $end
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$var wire 1 j \inst14|inst2~5_combout\ $end
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$var wire 1 k \inst14|inst2~6_combout\ $end
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$var wire 1 l \I10~input_o\ $end
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$var wire 1 m \I8~input_o\ $end
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$var wire 1 n \I9~input_o\ $end
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$var wire 1 o \inst14|inst2~0_combout\ $end
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$var wire 1 p \I11~input_o\ $end
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$var wire 1 q \inst14|inst2~1_combout\ $end
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$var wire 1 r \inst14|inst2~9_combout\ $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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