16 lines
306 B
VHDL
16 lines
306 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity EqCmp8 is
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port
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(
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input0 : in std_logic_vector(7 downto 0);
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input1 : in std_logic_vector(7 downto 0);
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cmpOut : out std_logic
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);
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end EqCmp8;
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architecture Behavioral of EqCmp8 is
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begin
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cmpOut <= '1' when (input0 = input1) else '0';
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end Behavioral; |