TiagoRG
/
uaveiro-leci
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
uaveiro-leci/1ano/isd/quartus-projects/Teste/db/Teste1.map.qmsg

16 lines
6.9 KiB
Plaintext
Raw Blame History

{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1669986134544 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1669986134544 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 2 13:02:14 2022 " "Processing started: Fri Dec 2 13:02:14 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1669986134544 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669986134544 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Teste1 -c Teste1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off Teste1 -c Teste1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669986134545 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1669986134656 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1669986134657 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Teste1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Teste1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Teste1 " "Found entity 1: Teste1" { } { { "Teste1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Teste1.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1669986140555 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669986140555 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Teste3.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Teste3.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Teste3 " "Found entity 1: Teste3" { } { { "Teste3.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Teste3.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1669986140556 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669986140556 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Teste3 " "Elaborating entity \"Teste3\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1669986140582 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Teste1 Teste1:inst " "Elaborating entity \"Teste1\" for hierarchy \"Teste1:inst\"" { } { { "Teste3.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Teste3.bdf" { { 152 504 600 344 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1669986140584 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74153 Teste1:inst\|74153:inst " "Elaborating entity \"74153\" for hierarchy \"Teste1:inst\|74153:inst\"" { } { { "Teste1.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Teste1.bdf" { { 176 416 536 400 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1669986140586 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "Teste1:inst\|74153:inst " "Elaborated megafunction instantiation \"Teste1:inst\|74153:inst\"" { } { { "Teste1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Teste1.bdf" { { 176 416 536 400 "inst" "" } } } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1669986140586 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1669986140894 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1669986141136 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1669986141136 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "6 " "Implemented 6 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1669986141153 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1669986141153 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1669986141153 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1669986141153 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "398 " "Peak virtual memory: 398 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1669986141158 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 2 13:02:21 2022 " "Processing ended: Fri Dec 2 13:02:21 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1669986141158 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1669986141158 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:19 " "Total CPU time (on all processors): 00:00:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1669986141158 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1669986141158 ""}
Reference in New Issue View Git Blame Copy Permalink