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uaveiro-leci/1ano/2semestre/lsd/aula01/part2/db
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TiagoRG 651502a8df
LSD: aula01 part2 finished 		2023-03-01 12:17:08 +00:00
..
AND2Gate.(0).cnf.cdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.(0).cnf.hdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.(1).cnf.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.(1).cnf.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.(2).cnf.cdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.(2).cnf.hdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.(3).cnf.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.(3).cnf.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.(4).cnf.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.(4).cnf.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.asm.qmsg LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.asm.rdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.asm_labs.ddb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.cbx.xml LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.cmp.bpm LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.cmp.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.cmp.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.cmp.idb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.cmp.logdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.cmp.rdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.cmp_merge.kpt LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.db_info LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.eda.qmsg LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.fit.qmsg LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.hier_info LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.hif LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.lpc.html LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.lpc.rdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.lpc.txt LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.map.ammdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.map.bpm LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.map.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.map.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.map.kpt LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.map.qmsg LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.map.rdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.map_bb.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.map_bb.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.pre_map.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.root_partition.map.reg_db.cdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.routing.rdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.rtlv.hdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.rtlv_sg.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.rtlv_sg_swap.cdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.sld_design_entry.sci LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.sld_design_entry_dsc.sci LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.smart_action.txt LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.sta.qmsg LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.sta.rdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.sta_cmp.7_slow_1200mv_85c.tdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.tis_db_list.ddb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
AND2Gate.tiscmp.fast_1200mv_0c.ddb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.tiscmp.slow_1200mv_0c.ddb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.tiscmp.slow_1200mv_85c.ddb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.tmw_info LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate.vpr.ammdb LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
AND2Gate_partition_pins.json LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
VHDLDemo.map_bb.logdb LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
prev_cmp_VHDLDemo.qmsg LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00