uaveiro-leci/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_vhd.sdo

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// Copyright (C) 2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
//
// Device: Altera EP4CE6E22C6 Package TQFP144
//
//
// This file contains Slow Corner delays for the design using part EP4CE6E22C6,
// with speed grade 6, core voltage 1.2VmV, and temperature 85 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "Dec2_4")
(DATE "11/04/2022 15:08:53")
(VENDOR "Altera")
(PROGRAM "Quartus Prime")
(VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE \\Y3\~output\\)
(DELAY
(ABSOLUTE
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(IOPATH i o (2533:2533:2533) (2516:2516:2516))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE \\Y2\~output\\)
(DELAY
(ABSOLUTE
(PORT i (991:991:991) (1012:1012:1012))
(IOPATH i o (2533:2533:2533) (2516:2516:2516))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE \\Y1\~output\\)
(DELAY
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(IOPATH i o (2627:2627:2627) (2603:2603:2603))
)
)
)
(CELL
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(INSTANCE \\Y0\~output\\)
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)
)
)
(CELL
(CELLTYPE "cycloneive_io_ibuf")
(INSTANCE \\E1\~input\\)
(DELAY
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)
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)
(CELL
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(INSTANCE \\X1\~input\\)
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)
(CELL
(CELLTYPE "cycloneive_io_ibuf")
(INSTANCE \\X0\~input\\)
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(CELL
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(INSTANCE \\E0L\~input\\)
(DELAY
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)
(CELL
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(INSTANCE inst)
(DELAY
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(PORT datab (3049:3049:3049) (3301:3301:3301))
(PORT datac (803:803:803) (816:816:816))
(PORT datad (3063:3063:3063) (3333:3333:3333))
(IOPATH dataa combout (354:354:354) (349:349:349))
(IOPATH datab combout (381:381:381) (380:380:380))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE inst1)
(DELAY
(ABSOLUTE
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(IOPATH dataa combout (341:341:341) (319:319:319))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE inst2)
(DELAY
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(PORT datab (3049:3049:3049) (3301:3301:3301))
(PORT datac (801:801:801) (812:812:812))
(PORT datad (3061:3061:3061) (3332:3332:3332))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE inst3)
(DELAY
(ABSOLUTE
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(PORT datab (3049:3049:3049) (3301:3301:3301))
(PORT datac (801:801:801) (811:811:811))
(PORT datad (3061:3061:3061) (3332:3332:3332))
(IOPATH dataa combout (327:327:327) (347:347:347))
(IOPATH datab combout (331:331:331) (342:342:342))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
)