17 lines
1.1 KiB
Plaintext
17 lines
1.1 KiB
Plaintext
vendor_name = ModelSim
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/db/AND2Gate.cbx.xml
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design_name = hard_block
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design_name = GateDemo
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instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1
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instance = comp, \LEDR[1]~output\, LEDR[1]~output, GateDemo, 1
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instance = comp, \SW[1]~input\, SW[1]~input, GateDemo, 1
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instance = comp, \SW[0]~input\, SW[0]~input, GateDemo, 1
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instance = comp, \system_core|outPort\, system_core|outPort, GateDemo, 1
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