uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim
TiagoRG 4d23ebbdc1
LSD aula01 initial commit, base VHDL files, to be finished along the hardware
2023-02-20 22:37:38 +00:00
..
work LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
GateDemo.do LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
GateDemo.msim.vcd LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
GateDemo.sft LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
GateDemo.vho LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
GateDemo.vwf.vht LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
GateDemo_20230218145515.sim.vwf LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
GateDemo_modelsim.xrf LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
transcript LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
vwf_sim_transcript LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00