227 lines
5.3 KiB
VHDL
227 lines
5.3 KiB
VHDL
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- *****************************************************************************
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-- This file contains a Vhdl test bench with test vectors .The test vectors
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-- are exported from a vector file in the Quartus Waveform Editor and apply to
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-- the top level entity of the current Quartus project .The user can use this
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-- testbench to simulate his design using a third-party simulation tool .
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-- *****************************************************************************
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-- Generated on "03/17/2023 12:07:03"
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-- Vhdl Test Bench(with test vectors) for design : CmpN
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--
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-- Simulation tool : 3rd Party
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY CmpN_vhd_vec_tst IS
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END CmpN_vhd_vec_tst;
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ARCHITECTURE CmpN_arch OF CmpN_vhd_vec_tst IS
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-- constants
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-- signals
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SIGNAL equal : STD_LOGIC;
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SIGNAL input0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL input1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL ltSigned : STD_LOGIC;
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SIGNAL ltUnsigned : STD_LOGIC;
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SIGNAL notEqual : STD_LOGIC;
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COMPONENT CmpN
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PORT (
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equal : OUT STD_LOGIC;
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input0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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input1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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ltSigned : OUT STD_LOGIC;
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ltUnsigned : OUT STD_LOGIC;
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notEqual : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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i1 : CmpN
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PORT MAP (
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-- list connections between master ports and signals
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equal => equal,
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input0 => input0,
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input1 => input1,
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ltSigned => ltSigned,
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ltUnsigned => ltUnsigned,
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notEqual => notEqual
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);
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-- input0[7]
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t_prcs_input0_7: PROCESS
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BEGIN
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input0(7) <= '0';
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WAIT FOR 80000 ps;
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input0(7) <= '1';
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WAIT FOR 80000 ps;
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input0(7) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_7;
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-- input0[6]
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t_prcs_input0_6: PROCESS
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BEGIN
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input0(6) <= '1';
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WAIT FOR 80000 ps;
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input0(6) <= '0';
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WAIT FOR 80000 ps;
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input0(6) <= '1';
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WAIT FOR 80000 ps;
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input0(6) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_6;
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-- input0[5]
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t_prcs_input0_5: PROCESS
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BEGIN
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input0(5) <= '1';
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WAIT FOR 80000 ps;
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input0(5) <= '0';
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WAIT FOR 80000 ps;
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input0(5) <= '1';
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WAIT FOR 80000 ps;
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input0(5) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_5;
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-- input0[4]
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t_prcs_input0_4: PROCESS
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BEGIN
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input0(4) <= '1';
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WAIT FOR 80000 ps;
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input0(4) <= '0';
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WAIT FOR 80000 ps;
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input0(4) <= '1';
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WAIT FOR 80000 ps;
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input0(4) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_4;
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-- input0[3]
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t_prcs_input0_3: PROCESS
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BEGIN
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input0(3) <= '1';
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WAIT FOR 80000 ps;
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input0(3) <= '0';
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WAIT FOR 80000 ps;
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input0(3) <= '1';
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WAIT FOR 80000 ps;
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input0(3) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_3;
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-- input0[2]
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t_prcs_input0_2: PROCESS
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BEGIN
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input0(2) <= '1';
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WAIT FOR 80000 ps;
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input0(2) <= '0';
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WAIT FOR 80000 ps;
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input0(2) <= '1';
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WAIT FOR 80000 ps;
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input0(2) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_2;
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-- input0[1]
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t_prcs_input0_1: PROCESS
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BEGIN
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input0(1) <= '1';
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WAIT FOR 80000 ps;
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input0(1) <= '0';
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WAIT FOR 80000 ps;
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input0(1) <= '1';
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WAIT FOR 80000 ps;
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input0(1) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_1;
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-- input0[0]
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t_prcs_input0_0: PROCESS
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BEGIN
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input0(0) <= '1';
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WAIT FOR 80000 ps;
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input0(0) <= '0';
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WAIT FOR 80000 ps;
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input0(0) <= '1';
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WAIT FOR 80000 ps;
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input0(0) <= '0';
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WAIT;
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END PROCESS t_prcs_input0_0;
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-- input1[7]
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t_prcs_input1_7: PROCESS
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BEGIN
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input1(7) <= '1';
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WAIT FOR 80000 ps;
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input1(7) <= '0';
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WAIT FOR 80000 ps;
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input1(7) <= '1';
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WAIT FOR 80000 ps;
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input1(7) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_7;
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-- input1[6]
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t_prcs_input1_6: PROCESS
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BEGIN
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input1(6) <= '1';
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WAIT FOR 80000 ps;
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input1(6) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_6;
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-- input1[5]
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t_prcs_input1_5: PROCESS
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BEGIN
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input1(5) <= '1';
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WAIT FOR 80000 ps;
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input1(5) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_5;
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-- input1[4]
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t_prcs_input1_4: PROCESS
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BEGIN
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input1(4) <= '1';
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WAIT FOR 80000 ps;
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input1(4) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_4;
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-- input1[3]
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t_prcs_input1_3: PROCESS
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BEGIN
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input1(3) <= '1';
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WAIT FOR 80000 ps;
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input1(3) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_3;
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-- input1[2]
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t_prcs_input1_2: PROCESS
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BEGIN
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input1(2) <= '1';
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WAIT FOR 80000 ps;
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input1(2) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_2;
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-- input1[1]
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t_prcs_input1_1: PROCESS
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BEGIN
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input1(1) <= '1';
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WAIT FOR 80000 ps;
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input1(1) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_1;
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-- input1[0]
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t_prcs_input1_0: PROCESS
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BEGIN
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input1(0) <= '1';
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WAIT FOR 80000 ps;
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input1(0) <= '0';
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WAIT;
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END PROCESS t_prcs_input1_0;
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END CmpN_arch;
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