uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register.vhd.bak

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Register8 is
	port
	(
		dataIn  : in  std_logic_vector(7 downto 0);
		clk     : in  std_logic;
		dataOut : out std_logic_vector(7 downto 0)
	);
end Register8;