53 lines
2.2 KiB
VHDL
53 lines
2.2 KiB
VHDL
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- *****************************************************************************
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-- This file contains a Vhdl test bench with test vectors .The test vectors
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-- are exported from a vector file in the Quartus Waveform Editor and apply to
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-- the top level entity of the current Quartus project .The user can use this
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-- testbench to simulate his design using a third-party simulation tool .
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-- *****************************************************************************
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-- Generated on "03/08/2023 11:38:17"
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-- Vhdl Test Bench(with test vectors) for design : AdderDemo
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--
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-- Simulation tool : 3rd Party
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY AdderDemo_vhd_vec_tst IS
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END AdderDemo_vhd_vec_tst;
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ARCHITECTURE AdderDemo_arch OF AdderDemo_vhd_vec_tst IS
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-- constants
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-- signals
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SIGNAL LEDR : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL SW : STD_LOGIC_VECTOR(7 DOWNTO 0);
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COMPONENT AdderDemo
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PORT (
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LEDR : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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i1 : AdderDemo
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PORT MAP (
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-- list connections between master ports and signals
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LEDR => LEDR,
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SW => SW
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);
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END AdderDemo_arch;
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