52 lines
1.2 KiB
VHDL
52 lines
1.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity SeqShiftUnit is
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port
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(
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clk : in std_logic;
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dataIn : in std_logic_vector(7 downto 0);
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siLeft : in std_logic;
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siRight : in std_logic;
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loadEn : in std_logic;
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rotate : in std_logic;
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dirLeft : in std_logic;
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shArith : in std_logic;
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dataOut : out std_logic_vector(7 downto 0)
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);
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end SeqShiftUnit;
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architecture Behavioral of SeqShiftUnit is
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signal s_shiftReg : std_logic_vector(7 downto 0);
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begin
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process (clk)
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begin
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if (falling_edge(clk)) then
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if (loadEn = '1') then
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s_shiftReg <= dataIn;
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elsif (rotate = '1') then
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if (dirLeft = '1') then
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s_shiftReg <= s_shiftReg(6 downto 0) & s_shiftReg(7);
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else
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s_shiftReg <= s_shiftReg(0) & s_shiftReg(7 downto 1);
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end if;
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elsif (shArith = '1') then
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if (dirLeft = '1') then
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s_shiftReg <= s_shiftReg(6 downto 0) & '0';
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else
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s_shiftReg <= s_shiftReg(7) & s_shiftReg(7 downto 1);
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end if;
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else
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if (dirLeft = '1') then
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s_shiftReg <= s_shiftReg(6 downto 0) & siLeft;
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else
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s_shiftReg <= siRight & s_shiftReg(7 downto 1);
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end if;
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end if;
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end if;
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end process;
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dataOut <= s_ShiftReg;
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end Behavioral; |